diff options
| author | Hiroshi Doyu <hdoyu@nvidia.com> | 2013-07-01 09:06:58 +0300 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:40:45 -0700 |
| commit | 9792728eec13e578f97ff46a2014e0603d2d1f19 (patch) | |
| tree | 5f541306c230fa01588b1e708be69a84d89dd52b /drivers/iommu | |
| parent | a85980637d31d696652e0786c1effd2c5da711fb (diff) | |
iommu/tegra: smmu: Fix {TLB,PTC} reset value per SoC
TLB_RR_ARB and PTC_REQ_LIMIT is only valid for T124.
Bug 1320358
Bug 1315906
Change-Id: I1d57ac1fb525629966987483b6c8c871c4ed2d4e
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/260878
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/tegra-smmu.c | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 3cb0e0e29cc0..c916be780611 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -73,11 +73,13 @@ enum { #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29) #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10 -#define SMMU_TLB_CONFIG_RESET_VAL 0x30000010 +#define SMMU_TLB_CONFIG_RESET_VAL 0x20000010 +#define SMMU_TLB_RR_ARB (1 << 28) #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29) #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f -#define SMMU_PTC_CONFIG_RESET_VAL 0x2800003f +#define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f +#define SMMU_PTC_REQ_LIMIT (8 << 24) #define SMMU_PTB_ASID 0x1c #define SMMU_PTB_ASID_CURRENT_SHIFT 0 @@ -562,8 +564,19 @@ static void smmu_setup_regs(struct smmu_device *smmu) smmu_write(smmu, smmu->asid_security[i], smmu_asid_security_ofs[i]); - smmu_write(smmu, SMMU_TLB_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_TLB)); - smmu_write(smmu, SMMU_PTC_CONFIG_RESET_VAL, SMMU_CACHE_CONFIG(_PTC)); + val = SMMU_PTC_CONFIG_RESET_VAL; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) && + (tegra_get_chipid() == TEGRA_CHIPID_TEGRA12)) + val |= SMMU_PTC_REQ_LIMIT; + + smmu_write(smmu, val, SMMU_CACHE_CONFIG(_PTC)); + + val = SMMU_TLB_CONFIG_RESET_VAL; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) && + (tegra_get_chipid() == TEGRA_CHIPID_TEGRA12)) + val |= SMMU_TLB_RR_ARB; + + smmu_write(smmu, val, SMMU_CACHE_CONFIG(_TLB)); if (IS_ENABLED(CONFIG_ARCH_TEGRA_12x_SOC) && (tegra_get_chipid() == TEGRA_CHIPID_TEGRA12)) |