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authorHiroshi DOYU <hdoyu@nvidia.com>2012-03-15 12:10:17 +0200
committerVarun Colbert <vcolbert@nvidia.com>2012-08-01 17:48:22 -0700
commitb8f610d8a591d0287d8a996915b3dfae6d8672da (patch)
tree514c00049e91f7872e2d097e0a5fe2ec7b1a300a /drivers/iommu
parentb147a3da3e867fc4279fec7fa59655f1eebbe6d6 (diff)
iommu/tegra: smmu: Introduce TEGRA_IOMMU_SMMU_LINEAR
IOVA liner mapping for RAM can be removed with this config disabled. This CONFIG_TEGRA_IOMMU_SMMU_LINEAR will be removed eventually. All IOMMU'able drivers should support DMA API correctly during transition period. phys_to_virt() won't be used with IOMMU'able H/W. Change-Id: I0d6f86cf9974a3d2e9ef1c5286461f2ea2cd1918 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/118708 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/Kconfig11
-rw-r--r--drivers/iommu/tegra-smmu.c11
2 files changed, 20 insertions, 2 deletions
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 3bd9fff5c589..b736809102df 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -162,4 +162,15 @@ config TEGRA_IOMMU_SMMU
space through the SMMU (System Memory Management Unit)
hardware included on Tegra SoCs.
+config TEGRA_IOMMU_SMMU_LINEAR
+ bool "Physical RAM IOVA Liner Mapping Support"
+ depends on TEGRA_IOMMU_SMMU
+ default y
+ help
+ Enables support for linear mapping between physical address
+ and IO virtual address for RAM. With this enabled, H/W can
+ expect virt_to_phys() to work even if it's behined the
+ IOMMU'able bus. Otherwise DMA API should be used correctly
+ in device drivers.
+
endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index 915763c748f1..780a77b8a219 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -183,10 +183,17 @@ enum {
#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
#define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
-#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
+#define _PDE_VACANT(pdn) (0)
#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
-#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
+#define _PTE_VACANT(addr) (0)
+
+#ifdef CONFIG_TEGRA_IOMMU_SMMU_LINEAR
+#undef _PDE_VACANT(pdn)
+#undef _PTE_VACANT(addr)
+#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
+#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
+#endif
#define SMMU_MK_PDIR(page, attr) \
((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))