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authorNiklas Cassel <niklas.cassel@axis.com>2018-02-26 22:47:06 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-05-30 07:50:49 +0200
commit5b3b32d061477e99d0805197930ad60dd51909d6 (patch)
tree07e56f0aef66f8f53160de2d27b98215b5c02c84 /drivers/irqchip/irq-omap-intc.c
parent82aad32b4aad92244bc7b8e4cd1210253785fe03 (diff)
net: stmmac: ensure that the MSS desc is the last desc to set the own bit
[ Upstream commit 15d2ee42a3087089e73ad52fd8c1b37ab496b87c ] A dma_wmb() is used to guarantee the ordering, with respect to other writes, to cache coherent DMA memory. There is a dma_wmb() in prepare_tx_desc()/prepare_tso_tx_desc() which ensures that TDES0/1/2 is written before TDES3 (which contains the own bit), for First Desc. However, in the rare case that MSS changes, there will be a MSS context descriptor in front of the regular DMA descriptors: <MSS desc> <- DMA Next Descriptor <First Desc> <desc n> <Last Desc> Thus, for this special case, we need a dma_wmb() after prepare_tso_tx_desc()/before writing the own bit to the MSS desc, so that we flush the write to TDES3 for First Desc, in order to ensure that the MSS descriptor is the last descriptor to set the own bit. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/irqchip/irq-omap-intc.c')
0 files changed, 0 insertions, 0 deletions