diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2015-09-30 12:01:16 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2015-10-09 22:16:55 +0100 |
| commit | 76e52dd01cabc340c1a58f540c9d6bf0e79c6b23 (patch) | |
| tree | da092d585e599c04a2e34ddcebbdf002d1c03c4d /drivers/irqchip | |
| parent | 963fcd40958711cecf9e9a1a8525f88b782d6a98 (diff) | |
irqchip/gic: Warn if GICv3 system registers are enabled
When using a GICv3 in compatibility (v2) mode, having GICv3 system
register access enabled is not really compliant with the architecture.
Warn if the firmware (or the hypervisor) has been lazy.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip')
| -rw-r--r-- | drivers/irqchip/irq-gic.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index d0ce7ed1ac8a..a9f23cfa9c96 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -51,6 +51,19 @@ #include "irq-gic-common.h" +#ifdef CONFIG_ARM64 +#include <asm/cpufeature.h> + +static void gic_check_cpu_features(void) +{ + WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), + TAINT_CPU_OUT_OF_SPEC, + "GICv3 system registers enabled, broken firmware!\n"); +} +#else +#define gic_check_cpu_features() do { } while(0) +#endif + union gic_base { void __iomem *common_base; void __percpu * __iomem *percpu_base; @@ -987,6 +1000,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, BUG_ON(gic_nr >= MAX_GIC_NR); + gic_check_cpu_features(); + gic = &gic_data[gic_nr]; #ifdef CONFIG_GIC_NON_BANKED if (percpu_offset) { /* Frankein-GIC without banked registers... */ |