Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next

Pull networking merge from David Miller:
 "1) Move ixgbe driver over to purely page based buffering on receive.
     From Alexander Duyck.

  2) Add receive packet steering support to e1000e, from Bruce Allan.

  3) Convert TCP MD5 support over to RCU, from Eric Dumazet.

  4) Reduce cpu usage in handling out-of-order TCP packets on modern
     systems, also from Eric Dumazet.

  5) Support the IP{,V6}_UNICAST_IF socket options, making the wine
     folks happy, from Erich Hoover.

  6) Support VLAN trunking from guests in hyperv driver, from Haiyang
     Zhang.

  7) Support byte-queue-limtis in r8169, from Igor Maravic.

  8) Outline code intended for IP_RECVTOS in IP_PKTOPTIONS existed but
     was never properly implemented, Jiri Benc fixed that.

  9) 64-bit statistics support in r8169 and 8139too, from Junchang Wang.

  10) Support kernel side dump filtering by ctmark in netfilter
      ctnetlink, from Pablo Neira Ayuso.

  11) Support byte-queue-limits in gianfar driver, from Paul Gortmaker.

  12) Add new peek socket options to assist with socket migration, from
      Pavel Emelyanov.

  13) Add sch_plug packet scheduler whose queue is controlled by
      userland daemons using explicit freeze and release commands.  From
      Shriram Rajagopalan.

  14) Fix FCOE checksum offload handling on transmit, from Yi Zou."

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1846 commits)
  Fix pppol2tp getsockname()
  Remove printk from rds_sendmsg
  ipv6: fix incorrent ipv6 ipsec packet fragment
  cpsw: Hook up default ndo_change_mtu.
  net: qmi_wwan: fix build error due to cdc-wdm dependecy
  netdev: driver: ethernet: Add TI CPSW driver
  netdev: driver: ethernet: add cpsw address lookup engine support
  phy: add am79c874 PHY support
  mlx4_core: fix race on comm channel
  bonding: send igmp report for its master
  fs_enet: Add MPC5125 FEC support and PHY interface selection
  net: bpf_jit: fix BPF_S_LDX_B_MSH compilation
  net: update the usage of CHECKSUM_UNNECESSARY
  fcoe: use CHECKSUM_UNNECESSARY instead of CHECKSUM_PARTIAL on tx
  net: do not do gso for CHECKSUM_UNNECESSARY in netif_needs_gso
  ixgbe: Fix issues with SR-IOV loopback when flow control is disabled
  net/hyperv: Fix the code handling tx busy
  ixgbe: fix namespace issues when FCoE/DCB is not enabled
  rtlwifi: Remove unused ETH_ADDR_LEN defines
  igbvf: Use ETH_ALEN
  ...

Fix up fairly trivial conflicts in drivers/isdn/gigaset/interface.c and
drivers/net/usb/{Kconfig,qmi_wwan.c} as per David.

1 files changed, 78 insertions, 78 deletions

diff --git a/drivers/isdn/hisax/jade.h b/drivers/isdn/hisax/jade.h
index 29055e1ee381..4b98096a5858 100644
--- a/drivers/isdn/hisax/jade.h
+++ b/drivers/isdn/hisax/jade.h
@@ -4,7 +4,7 @@
  *
  * Author       Roland Klabunde
  * Copyright    by Roland Klabunde   <R.Klabunde@Berkom.de>
- * 
+ *
  * This software may be used and distributed according to the terms
  * of the GNU General Public License, incorporated herein by reference.
  *
@@ -16,111 +16,111 @@
 
 /* Special registers for access to indirect accessible JADE regs */
 #define	DIRECT_IO_JADE	0x0000	/* Jade direct io access area */
-#define	COMM_JADE	0x0040	/* Jade communication area */	   	
+#define	COMM_JADE	0x0040	/* Jade communication area */
 
 /********************************************************************/
-/* JADE-HDLC registers         									    */
+/* JADE-HDLC registers										    */
 /********************************************************************/
-#define jade_HDLC_RFIFO	   				0x00				   /* R */
-#define jade_HDLC_XFIFO	   				0x00				   /* W */
-
-#define	jade_HDLC_STAR	   				0x20				   /* R */
-	#define	jadeSTAR_XDOV				0x80
-	#define	jadeSTAR_XFW 				0x40 /* Does not work*/
-	#define	jadeSTAR_XCEC 				0x20
-	#define	jadeSTAR_RCEC				0x10
-	#define	jadeSTAR_BSY 				0x08
-	#define	jadeSTAR_RNA 				0x04
-	#define	jadeSTAR_STR 				0x02
-	#define	jadeSTAR_STX				0x01
-
-#define	jade_HDLC_XCMD	   				0x20				   /* W */
-	#define	jadeXCMD_XF				0x80
-	#define	jadeXCMD_XME				0x40
-	#define	jadeXCMD_XRES				0x20
-	#define	jadeXCMD_STX				0x01
-
-#define	jade_HDLC_RSTA	   				0x21				   /* R */
-    #define	jadeRSTA_VFR				0x80
-    #define	jadeRSTA_RDO				0x40
-    #define	jadeRSTA_CRC				0x20
-    #define	jadeRSTA_RAB				0x10
-    #define	jadeRSTA_MASK			   	0xF0
+#define jade_HDLC_RFIFO					0x00				   /* R */
+#define jade_HDLC_XFIFO					0x00				   /* W */
+
+#define	jade_HDLC_STAR					0x20				   /* R */
+#define	jadeSTAR_XDOV				0x80
+#define	jadeSTAR_XFW				0x40 /* Does not work*/
+#define	jadeSTAR_XCEC				0x20
+#define	jadeSTAR_RCEC				0x10
+#define	jadeSTAR_BSY				0x08
+#define	jadeSTAR_RNA				0x04
+#define	jadeSTAR_STR				0x02
+#define	jadeSTAR_STX				0x01
+
+#define	jade_HDLC_XCMD					0x20				   /* W */
+#define	jadeXCMD_XF				0x80
+#define	jadeXCMD_XME				0x40
+#define	jadeXCMD_XRES				0x20
+#define	jadeXCMD_STX				0x01
+
+#define	jade_HDLC_RSTA					0x21				   /* R */
+#define	jadeRSTA_VFR				0x80
+#define	jadeRSTA_RDO				0x40
+#define	jadeRSTA_CRC				0x20
+#define	jadeRSTA_RAB				0x10
+#define	jadeRSTA_MASK				0xF0
 
 #define	jade_HDLC_MODE					0x22				   /* RW*/
-    #define	jadeMODE_TMO				0x80
-    #define	jadeMODE_RAC				0x40
-    #define	jadeMODE_XAC				0x20
-    #define	jadeMODE_TLP				0x10
-    #define	jadeMODE_ERFS				0x02
-    #define	jadeMODE_ETFS				0x01
+#define	jadeMODE_TMO				0x80
+#define	jadeMODE_RAC				0x40
+#define	jadeMODE_XAC				0x20
+#define	jadeMODE_TLP				0x10
+#define	jadeMODE_ERFS				0x02
+#define	jadeMODE_ETFS				0x01
 
 #define	jade_HDLC_RBCH					0x24				   /* R */
 
-#define	jade_HDLC_RBCL	 				0x25				   /* R */
-#define	jade_HDLC_RCMD	 				0x25				   /* W */
-	#define	jadeRCMD_RMC 				0x80
-	#define	jadeRCMD_RRES				0x40
-	#define	jadeRCMD_RMD				0x20
-	#define	jadeRCMD_STR				0x02
+#define	jade_HDLC_RBCL					0x25				   /* R */
+#define	jade_HDLC_RCMD					0x25				   /* W */
+#define	jadeRCMD_RMC				0x80
+#define	jadeRCMD_RRES				0x40
+#define	jadeRCMD_RMD				0x20
+#define	jadeRCMD_STR				0x02
 
 #define	jade_HDLC_CCR0					0x26				   /* RW*/
-	#define	jadeCCR0_PU  				0x80
-	#define	jadeCCR0_ITF				0x40
-	#define	jadeCCR0_C32				0x20
-	#define	jadeCCR0_CRL				0x10
-	#define	jadeCCR0_RCRC				0x08
-	#define	jadeCCR0_XCRC				0x04
-	#define	jadeCCR0_RMSB				0x02
-	#define	jadeCCR0_XMSB				0x01
+#define	jadeCCR0_PU				0x80
+#define	jadeCCR0_ITF				0x40
+#define	jadeCCR0_C32				0x20
+#define	jadeCCR0_CRL				0x10
+#define	jadeCCR0_RCRC				0x08
+#define	jadeCCR0_XCRC				0x04
+#define	jadeCCR0_RMSB				0x02
+#define	jadeCCR0_XMSB				0x01
 
 #define	jade_HDLC_CCR1					0x27				   /* RW*/
-    #define	jadeCCR1_RCS0				0x80
-    #define	jadeCCR1_RCONT				0x40
-    #define	jadeCCR1_RFDIS				0x20
-    #define	jadeCCR1_XCS0				0x10
-    #define	jadeCCR1_XCONT				0x08
-    #define	jadeCCR1_XFDIS				0x04
+#define	jadeCCR1_RCS0				0x80
+#define	jadeCCR1_RCONT				0x40
+#define	jadeCCR1_RFDIS				0x20
+#define	jadeCCR1_XCS0				0x10
+#define	jadeCCR1_XCONT				0x08
+#define	jadeCCR1_XFDIS				0x04
 
 #define	jade_HDLC_TSAR					0x28				   /* RW*/
 #define	jade_HDLC_TSAX					0x29				   /* RW*/
 #define	jade_HDLC_RCCR					0x2A				   /* RW*/
 #define	jade_HDLC_XCCR					0x2B				   /* RW*/
 
-#define	jade_HDLC_ISR 					0x2C				   /* R */
-#define	jade_HDLC_IMR 					0x2C				   /* W */
-	#define	jadeISR_RME					0x80
-	#define	jadeISR_RPF					0x40
-	#define	jadeISR_RFO					0x20
-	#define	jadeISR_XPR					0x10
-	#define	jadeISR_XDU					0x08
-	#define	jadeISR_ALLS				0x04
-
-#define jade_INT            			0x75
-    #define jadeINT_HDLC1   			0x02
-    #define jadeINT_HDLC2   			0x01
-    #define jadeINT_DSP				0x04
-#define jade_INTR            			0x70
+#define	jade_HDLC_ISR					0x2C				   /* R */
+#define	jade_HDLC_IMR					0x2C				   /* W */
+#define	jadeISR_RME					0x80
+#define	jadeISR_RPF					0x40
+#define	jadeISR_RFO					0x20
+#define	jadeISR_XPR					0x10
+#define	jadeISR_XDU					0x08
+#define	jadeISR_ALLS				0x04
+
+#define jade_INT				0x75
+#define jadeINT_HDLC1				0x02
+#define jadeINT_HDLC2				0x01
+#define jadeINT_DSP				0x04
+#define jade_INTR				0x70
 
 /********************************************************************/
-/* Indirect accessible JADE registers of common interest		   	*/
+/* Indirect accessible JADE registers of common interest			*/
 /********************************************************************/
 #define	jade_CHIPVERSIONNR				0x00 /* Does not work*/
 
-#define	jade_HDLCCNTRACCESS				0x10		
-	#define	jadeINDIRECT_HAH1			0x02
-	#define	jadeINDIRECT_HAH2			0x01
+#define	jade_HDLCCNTRACCESS				0x10
+#define	jadeINDIRECT_HAH1			0x02
+#define	jadeINDIRECT_HAH2			0x01
 
 #define	jade_HDLC1SERRXPATH				0x1D
 #define	jade_HDLC1SERTXPATH				0x1E
 #define	jade_HDLC2SERRXPATH				0x1F
 #define	jade_HDLC2SERTXPATH				0x20
-	#define	jadeINDIRECT_SLIN1			0x10
-	#define	jadeINDIRECT_SLIN0			0x08
-	#define	jadeINDIRECT_LMOD1			0x04
-	#define	jadeINDIRECT_LMOD0			0x02
-	#define	jadeINDIRECT_HHR			0x01
-	#define	jadeINDIRECT_HHX			0x01
+#define	jadeINDIRECT_SLIN1			0x10
+#define	jadeINDIRECT_SLIN0			0x08
+#define	jadeINDIRECT_LMOD1			0x04
+#define	jadeINDIRECT_LMOD0			0x02
+#define	jadeINDIRECT_HHR			0x01
+#define	jadeINDIRECT_HHX			0x01
 
 #define	jade_RXAUDIOCH1CFG				0x11
 #define	jade_RXAUDIOCH2CFG				0x14