diff options
| author | Sandor Yu <R01008@freescale.com> | 2014-05-16 14:08:46 +0800 |
|---|---|---|
| committer | Sandor Yu <R01008@freescale.com> | 2014-05-19 11:25:19 +0800 |
| commit | a303de79cbc8473ee4fff0f60fe473449bb7cd23 (patch) | |
| tree | f9f61afcd109a651fe58a461b41faed2b77c5979 /drivers/media | |
| parent | 8d3d76116e17db2f78021f88bad2d6615da6a544 (diff) | |
ENGR00313888 vadc: Enable Chroma AGC Control register
Add register LMAGC1 and CHAGC1 that missing in i.MX6sx RM.
Enable chroma AGC function.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Diffstat (limited to 'drivers/media')
| -rw-r--r-- | drivers/media/platform/mxc/capture/mxc_vadc.c | 6 | ||||
| -rw-r--r-- | drivers/media/platform/mxc/capture/mxc_vadc.h | 4 |
2 files changed, 7 insertions, 3 deletions
diff --git a/drivers/media/platform/mxc/capture/mxc_vadc.c b/drivers/media/platform/mxc/capture/mxc_vadc.c index 1c58d10fd925..05b2708d44b8 100644 --- a/drivers/media/platform/mxc/capture/mxc_vadc.c +++ b/drivers/media/platform/mxc/capture/mxc_vadc.c @@ -295,11 +295,11 @@ static void vdec_init(struct vadc_data *vadc) /* setup the luma agc for automatic gain. */ reg32_write(VDEC_LMAGC2, 0x5e); - reg32_write(VDEC_BASE + (0x40*4), 0x81); + reg32_write(VDEC_LMAGC1, 0x81); /* setup chroma agc */ - reg32_write(VDEC_CHAGC2, 0x09); - reg32_write(VDEC_BASE + (0x43*4), 0xa0); + reg32_write(VDEC_CHAGC2, 0xa0); + reg32_write(VDEC_CHAGC1, 0x01); /* setup the MV thresh lower nibble * setup the sync top cap, upper nibble */ diff --git a/drivers/media/platform/mxc/capture/mxc_vadc.h b/drivers/media/platform/mxc/capture/mxc_vadc.h index 91231be79561..6ed5eeb982d0 100644 --- a/drivers/media/platform/mxc/capture/mxc_vadc.h +++ b/drivers/media/platform/mxc/capture/mxc_vadc.h @@ -163,7 +163,9 @@ #define VDEC_BLSCRY_OFFSET 0x000000F4 #define VDEC_BLSCRCR_OFFSET 0x000000F8 #define VDEC_BLSCRCB_OFFSET 0x000000FC +#define VDEC_LMAGC1_OFFSET 0x00000100 #define VDEC_LMAGC2_OFFSET 0x00000104 +#define VDEC_CHAGC1_OFFSET 0x00000108 #define VDEC_CHAGC2_OFFSET 0x0000010C #define VDEC_MINTH_OFFSET 0x00000114 #define VDEC_VFRQOH_OFFSET 0x0000011C @@ -212,7 +214,9 @@ #define VDEC_BLSCRY (VDEC_BASE + VDEC_BLSCRY_OFFSET) #define VDEC_BLSCRCR (VDEC_BASE + VDEC_BLSCRCR_OFFSET) #define VDEC_BLSCRCB (VDEC_BASE + VDEC_BLSCRCB_OFFSET) +#define VDEC_LMAGC1 (VDEC_BASE + VDEC_LMAGC1_OFFSET) #define VDEC_LMAGC2 (VDEC_BASE + VDEC_LMAGC2_OFFSET) +#define VDEC_CHAGC1 (VDEC_BASE + VDEC_CHAGC1_OFFSET) #define VDEC_CHAGC2 (VDEC_BASE + VDEC_CHAGC2_OFFSET) #define VDEC_MINTH (VDEC_BASE + VDEC_MINTH_OFFSET) #define VDEC_VFRQOH (VDEC_BASE + VDEC_VFRQOH_OFFSET) |