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authorNathan Lord <nlord@nvidia.com>2011-02-14 18:54:03 -0800
committerVarun Colbert <vcolbert@nvidia.com>2011-02-15 18:40:27 -0800
commitd3b07f3a86353a37900a5928d1af518b01469b13 (patch)
treeb29c00932ee37575d22d2ccfc637625ae4c54397 /drivers/media
parent02e50de423e1f44158a01bfd59f00cd37d31ba5b (diff)
media: video: tegra: enable ov2710 manual exposure
Change-Id: I2b572a4fdfd83f7f9dc9b3f5b9244072cb240764 Reviewed-on: http://git-master/r/19528 Reviewed-by: Nathan Lord <nlord@nvidia.com> Tested-by: Nathan Lord <nlord@nvidia.com> Reviewed-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com> Reviewed-by: Chien-Yu Chen <chichen@nvidia.com> Reviewed-by: Patrick Shehane <pshehane@nvidia.com> Reviewed-by: Chan Vu Truong <jtruong@nvidia.com> Tested-by: Chan Vu Truong <jtruong@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/video/tegra/ov2710.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/media/video/tegra/ov2710.c b/drivers/media/video/tegra/ov2710.c
index 053760738ba2..5497b6cf213d 100644
--- a/drivers/media/video/tegra/ov2710.c
+++ b/drivers/media/video/tegra/ov2710.c
@@ -131,6 +131,8 @@ static struct ov2710_reg mode_1920x1080[] = {
{0x4301, 0xff},
{0x4303, 0x00},
{0x3a00, 0x78},
+ {0x3a18, 0x00}, /* AEC gain ceiling bit 8 pg 51 */
+ {0x3a19, 0xf8}, /* AEC gain ceiling pg 51 */
{0x300f, 0x88},
{0x3011, 0x28},
{0x3a1a, 0x06},
@@ -159,6 +161,15 @@ static struct ov2710_reg mode_1920x1080[] = {
{0x3a11, 0x90},
{0x3a1f, 0x10},
+ {0x350c, 0xff}, /* peak VTS reg, set to highest limit */
+ {0x350d, 0xff}, /* peak VTS reg, set to highest limit */
+ {0x3503, 0x07}, /* enable manual gain and manual exposure */
+ {0x3500, 0x00}, /* write default to AEC PK EXPO */
+ {0x3501, 0x00}, /* write default to AEC PK EXPO */
+ {0x3502, 0x02}, /* write default to AEC PK EXPO */
+ {0x350a, 0x00}, /* write default to manual gain reg */
+ {0x350b, 0x10}, /* write default to manual gain reg */
+
{OV2710_TABLE_END, 0x0000}
};
@@ -201,6 +212,8 @@ static struct ov2710_reg mode_1280x720[] = {
{0x4301, 0xff},
{0x4303, 0x00},
{0x3a00, 0x78},
+ {0x3a18, 0x00}, /* AEC gain ceiling bit 8 pg 51 */
+ {0x3a19, 0xf8}, /* AEC gain ceiling pg 51 */
{0x300f, 0x88},
{0x3011, 0x28},
{0x3a1a, 0x06},
@@ -265,6 +278,15 @@ static struct ov2710_reg mode_1280x720[] = {
{0x3a0a, 0x0b},
{0x3a0b, 0xa0},
+ {0x350c, 0xff}, /* peak VTS reg, set to highest limit */
+ {0x350d, 0xff}, /* peak VTS reg, set to highest limit */
+ {0x3503, 0x07}, /* enable manual gain and manual exposure */
+ {0x3500, 0x00}, /* write default to AEC PK EXPO */
+ {0x3501, 0x00}, /* write default to AEC PK EXPO */
+ {0x3502, 0x02}, /* write default to AEC PK EXPO */
+ {0x350a, 0x00}, /* write default to manual gain reg */
+ {0x350b, 0x10}, /* write default to manual gain reg */
+
{OV2710_TABLE_END, 0x0000}
};