diff options
| author | Tony Lindgren <tony@atomide.com> | 2015-06-01 19:22:10 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2015-06-01 19:22:10 -0600 |
| commit | 63aa945b1013c34b145dcf218d4ea323cbd93f86 (patch) | |
| tree | 867cc2a8675635cb286eeca8f4364bacdc3e97e1 /drivers/memory | |
| parent | e26081808edadfd257c6c9d81014e3b25e9a6118 (diff) | |
memory: omap-gpmc: Add Kconfig option for debug
We support decoding the bootloader values if DEBUG is defined.
But we also need to change the struct omap_hwmod flags to have
HWMOD_INIT_NO_RESET to avoid the GPMC being reset during the
boot. Otherwise just the default timings will be displayed
instead of the bootloader configured timings.
This also allows us to clean up the various GPMC related
hwmod flags. For debugging, we only need HWMOD_INIT_NO_RESET,
and HWMOD_INIT_NO_IDLE is not needed.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'drivers/memory')
| -rw-r--r-- | drivers/memory/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/memory/omap-gpmc.c | 6 |
2 files changed, 11 insertions, 3 deletions
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 868036f70f8f..8406c668ecdc 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -49,6 +49,14 @@ config OMAP_GPMC interfacing to a variety of asynchronous as well as synchronous memory drives like NOR, NAND, OneNAND, SRAM. +config OMAP_GPMC_DEBUG + bool + depends on OMAP_GPMC + help + Enables verbose debugging mostly to decode the bootloader provided + timings. Enable this during development to configure devices + connected to the GPMC bus. + config MVEBU_DEVBUS bool "Marvell EBU Device Bus Controller" default y diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index c94ea0d68746..8911e51d410a 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c @@ -403,7 +403,7 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) p->cycle2cyclediffcsen); } -#ifdef DEBUG +#ifdef CONFIG_OMAP_GPMC_DEBUG /** * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. * @cs: Chip Select Region @@ -612,7 +612,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max } l = gpmc_cs_read_reg(cs, reg); -#ifdef DEBUG +#ifdef CONFIG_OMAP_GPMC_DEBUG pr_info( "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, @@ -767,7 +767,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, clk_activation, GPMC_CD_FCLK); -#ifdef DEBUG +#ifdef CONFIG_OMAP_GPMC_DEBUG pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", cs, (div * gpmc_get_fclk_period()) / 1000, div); #endif |