diff options
| author | Balaji T K <balajitk@ti.com> | 2012-04-09 12:08:33 +0530 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2012-04-22 11:16:47 -0400 |
| commit | 03b5d924b926dd994b16f30f7a13bfb71ee0f478 (patch) | |
| tree | 37b5c8dec077bb04c408e4b6f4db8a9fcd2db9ab /drivers/mmc/host/omap_hsmmc.c | |
| parent | dba3c29ea4a1d5d544f59b94fd8a41662135e071 (diff) | |
mmc: omap_hsmmc: add DDR support
Add Dual data rate support for omap_hsmmc.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Venkatraman S <svenkatr@ti.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/host/omap_hsmmc.c')
| -rw-r--r-- | drivers/mmc/host/omap_hsmmc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index dfa6f87b6cc2..dc41b9e4299e 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -92,6 +92,7 @@ #define MSBS (1 << 5) #define BCE (1 << 1) #define FOUR_BIT (1 << 1) +#define DDR (1 << 19) #define DW8 (1 << 5) #define CC 0x1 #define TC 0x02 @@ -523,6 +524,10 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) u32 con; con = OMAP_HSMMC_READ(host->base, CON); + if (ios->timing == MMC_TIMING_UHS_DDR50) + con |= DDR; /* configure in DDR mode */ + else + con &= ~DDR; switch (ios->bus_width) { case MMC_BUS_WIDTH_8: OMAP_HSMMC_WRITE(host->base, CON, con | DW8); |