diff options
| author | Dong Aisheng <b29396@freescale.com> | 2013-10-21 15:27:40 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2013-10-30 09:56:03 +0800 |
| commit | 9a6f33c516a97020828458e48fb3cbde3781d8db (patch) | |
| tree | 65c391bbac46a89cd71b611911635bd51a7306cb /drivers/mmc/host/sdhci-esdhc-imx.c | |
| parent | 115b3c79a31d3cfecabe29beb5645521b08bc2b3 (diff) | |
mmc: sdhci-esdhc-imx: add DDR mode support for mx6
When DDR mode is enabled, the initial pre_div should be 2.
And the pre_div value should be changed accordingly
from
...
02h) Base clock divided by 4
01h) Base clock divided by 2
00h) Base clock divided by 1
to
..
02h) Base clock divided by 8
01h) Base clock divided by 4
00h) Base clock divided by 2
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'drivers/mmc/host/sdhci-esdhc-imx.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-esdhc-imx.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 6540934f2ab9..4b6cd9fa4808 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -38,6 +38,7 @@ #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) #define ESDHC_WTMK_LVL 0x44 #define ESDHC_MIX_CTRL 0x48 +#define ESDHC_MIX_CTRL_DDREN (1 << 3) #define ESDHC_MIX_CTRL_AC23EN (1 << 7) #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) @@ -152,6 +153,7 @@ struct pltfm_imx_data { WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ } multiblock_status; u32 uhs_mode; + u32 is_ddr; }; static struct platform_device_id imx_esdhc_devtype[] = { @@ -537,8 +539,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) * The reset on usdhc fails to clear MIX_CTRL register. * Do it manually here. */ - if (esdhc_is_usdhc(imx_data)) + if (esdhc_is_usdhc(imx_data)) { writel(0, host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 0; + } } } @@ -567,7 +571,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, goto out; } - if (esdhc_is_usdhc(imx_data)) + if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) pre_div = 1; temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); @@ -585,7 +589,10 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", clock, host->mmc->actual_clock); - pre_div >>= 1; + if (imx_data->is_ddr) + pre_div >>= 2; + else + pre_div >>= 1; div--; temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); @@ -851,6 +858,10 @@ static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) break; case MMC_TIMING_UHS_DDR50: imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; + writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | + ESDHC_MIX_CTRL_DDREN, + host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 1; break; } |