summaryrefslogtreecommitdiff
path: root/drivers/mmc/host/sdhci-pxav3.c
diff options
context:
space:
mode:
authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-10-21 11:22:34 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2014-11-10 12:40:30 +0100
commit668e84b20f7a76c7aacfc907906400b844561276 (patch)
tree345dbfe121314f0385551408ddb0f64204bfd355 /drivers/mmc/host/sdhci-pxav3.c
parent6a686c31324c9efd08ec1d42c5f5ecdfcd73a5f8 (diff)
mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling
commit bb8175a8aa42d731a840cd474e348ac3367eb5a0 ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. While the differentation may be useful, pxav3 SDHCI controller lacks a corresponding check in its custom .set_uhs_signaling callback for MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 to MMC_TIMING_UHS_DDR50 case. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-pxav3.c')
-rw-r--r--drivers/mmc/host/sdhci-pxav3.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 5036d7d39529..b55c807982fe 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
case MMC_TIMING_UHS_SDR104:
ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
break;
+ case MMC_TIMING_MMC_DDR52:
case MMC_TIMING_UHS_DDR50:
ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
break;