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authorHu Ziji <huziji@marvell.com>2017-04-28 10:35:15 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2017-04-28 12:33:14 +0200
commita04b9b47ae587e088439495f31ca740d92191a75 (patch)
treec4b0bfa99b6d310fdd723359e950673d9449419a /drivers/mmc/host/sdhci-xenon-phy.c
parent4cc59dffa9cb579613776cad5b777236210496d8 (diff)
mmc: sdhci-xenon: Fix default value of LOGIC_TIMING_ADJUST for eMMC5.0 PHY
The default value of LOGIC_TIMING_ADJUST register in eMMC 5.0 PHY is different from that in eMMC 5.1 PHY. Set the specific value for that register in eMMC 5.0 PHY. Signed-off-by: Hu Ziji <huziji@marvell.com> Reported-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-xenon-phy.c')
-rw-r--r--drivers/mmc/host/sdhci-xenon-phy.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
index d43841e9db14..6356781f1cca 100644
--- a/drivers/mmc/host/sdhci-xenon-phy.c
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -108,6 +108,7 @@
#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
(XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
+#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54
#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
#define XENON_LOGIC_TIMING_VALUE 0x00AA8977
@@ -130,6 +131,8 @@ struct xenon_emmc_phy_regs {
u16 logic_timing_adj;
/* DLL Update Enable bit */
u32 dll_update;
+ /* value in Logic Timing Adjustment register */
+ u32 logic_timing_val;
};
static const char * const phy_types[] = {
@@ -166,6 +169,7 @@ static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
.dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL,
.logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
.dll_update = XENON_DLL_UPDATE_STROBE_5_0,
+ .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE,
};
static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
@@ -176,6 +180,7 @@ static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
.dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL,
.logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,
.dll_update = XENON_DLL_UPDATE,
+ .logic_timing_val = XENON_LOGIC_TIMING_VALUE,
};
/*
@@ -607,7 +612,7 @@ static void xenon_emmc_phy_set(struct sdhci_host *host,
if (timing == MMC_TIMING_MMC_HS400)
/* Hardware team recommend a value for HS400 */
- sdhci_writel(host, XENON_LOGIC_TIMING_VALUE,
+ sdhci_writel(host, phy_regs->logic_timing_val,
phy_regs->logic_timing_adj);
else
xenon_emmc_phy_disable_data_strobe(host);