mmc: tegra: move postreset code to reset exit

move postreset code to reset exit.

Bug 1239457

Change-Id: Icb5f2f3f0dbf8c7d89c3eca7e7df13b71d2db1ce
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/207014
(cherry picked from commit bf93ff4541448e7560d866f00d129906d8aefceb)
Reviewed-on: http://git-master/r/209600
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

1 files changed, 137 insertions, 162 deletions

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 9223606c12bf..39f0e6543a92 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -43,21 +43,21 @@
 
 #include "sdhci-pltfm.h"
 
-#define SDHCI_VENDOR_CLOCK_CNTRL	0x100
-#define SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK	0x1
-#define SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE	0x8
-#define SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE	0x4
-#define SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT	8
-#define SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT	16
-#define SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT	24
-#define SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING		0x20
-
-#define SDHCI_VENDOR_MISC_CNTRL		0x120
-#define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT	0x8
-#define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT	0x10
-#define SDHCI_VENDOR_MISC_CNTRL_ENABLE_DDR50_SUPPORT	0x200
-#define SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0	0x20
-#define SDHCI_VENDOR_MISC_CNTRL_INFINITE_ERASE_TIMEOUT	0x1
+#define SDHCI_VNDR_CLK_CTRL	0x100
+#define SDHCI_VNDR_CLK_CTRL_SDMMC_CLK	0x1
+#define SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE	0x8
+#define SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE	0x4
+#define SDHCI_VNDR_CLK_CTRL_BASE_CLK_FREQ_SHIFT	8
+#define SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT	16
+#define SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT	24
+#define SDHCI_VNDR_CLK_CTRL_SDR50_TUNING		0x20
+
+#define SDHCI_VNDR_MISC_CTRL		0x120
+#define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT	0x8
+#define SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT	0x10
+#define SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT	0x200
+#define SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0	0x20
+#define SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT	0x1
 
 #define SDMMC_SDMEMCOMPPADCTRL	0x1E0
 #define SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_MASK	0xF
@@ -101,28 +101,15 @@ static unsigned int uhs_max_freq_MHz[] = {
 
 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
 static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock);
-static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci);
-#endif
-
-#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
-static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci);
-static unsigned int tegra11_sdhost_max_clk[4] = {
-	208000000,	104000000,	208000000,	208000000 };
 #endif
 
 static unsigned int tegra_sdhost_min_freq;
 static unsigned int tegra_sdhost_std_freq;
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-static unsigned int tegra3_sdhost_max_clk[4] = {
-	208000000,	104000000,	208000000,	104000000 };
-#endif
 
-struct tegra_sdhci_hw_ops{
+struct tegra_sdhci_hw_ops {
 	/* Set the internal clk and card clk.*/
 	void	(*set_card_clock)(struct sdhci_host *sdhci, unsigned int clock);
-	/* Post reset vendor registers configuration */
-	void	(*sdhost_init)(struct sdhci_host *sdhci);
 };
 
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
@@ -131,19 +118,42 @@ static struct tegra_sdhci_hw_ops tegra_2x_sdhci_ops = {
 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
 static struct tegra_sdhci_hw_ops tegra_3x_sdhci_ops = {
 	.set_card_clock = tegra_3x_sdhci_set_card_clock,
-	.sdhost_init = tegra3_sdhci_post_reset_init,
 };
 #else
 static struct tegra_sdhci_hw_ops tegra_11x_sdhci_ops = {
-        .sdhost_init = tegra11x_sdhci_post_reset_init,
 };
 #endif
 
+/* Erratum: Version register is invalid in HW */
 #define NVQUIRK_FORCE_SDHCI_SPEC_200		BIT(0)
+/* Erratum: Enable block gap interrupt detection */
 #define NVQUIRK_ENABLE_BLOCK_GAP_DET		BIT(1)
+/* Do not enable auto calibration if the platform doesn't support */
 #define NVQUIRK_DISABLE_AUTO_CALIBRATION	BIT(2)
-#define NVQUIRK_SET_CALIBRATION_OFFSETS	BIT(3)
+/* Set Calibration Offsets */
+#define NVQUIRK_SET_CALIBRATION_OFFSETS		BIT(3)
+/* Set Drive Strengths */
 #define NVQUIRK_SET_DRIVE_STRENGTH		BIT(4)
+/* Enable PADPIPE CLKEN */
+#define NVQUIRK_ENABLE_PADPIPE_CLKEN		BIT(5)
+/* DISABLE SPI_MODE CLKEN */
+#define NVQUIRK_DISABLE_SPI_MODE_CLKEN		BIT(6)
+/* Set tap delay */
+#define NVQUIRK_SET_TAP_DELAY			BIT(7)
+/* Set trim delay */
+#define NVQUIRK_SET_TRIM_DELAY			BIT(8)
+/* Enable SDHOST v3.0 support */
+#define NVQUIRK_ENABLE_SD_3_0			BIT(9)
+/* Enable SDR50 mode */
+#define NVQUIRK_ENABLE_SDR50			BIT(10)
+/* Enable SDR104 mode */
+#define NVQUIRK_ENABLE_SDR104			BIT(11)
+/*Enable DDR50 mode */
+#define NVQUIRK_ENABLE_DDR50			BIT(12)
+/* Enable Frequency Tuning for SDR50 mode */
+#define NVQUIRK_ENABLE_SDR50_TUNING		BIT(13)
+/* Enable Infinite Erase Timeout*/
+#define NVQUIRK_INFINITE_ERASE_TIMEOUT		BIT(14)
 
 struct sdhci_tegra_soc_data {
 	struct sdhci_pltfm_data *pdata;
@@ -296,7 +306,6 @@ static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
 
 	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
 			(reg == SDHCI_HOST_VERSION))) {
-		/* Erratum: Version register is invalid in HW. */
 		return SDHCI_SPEC_200;
 	}
 #endif
@@ -323,7 +332,6 @@ static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
 			(reg == SDHCI_INT_ENABLE))) {
-		/* Erratum: Must enable block gap interrupt detection */
 		u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
 		if (val & SDHCI_INT_CARD_INT)
 			gap_ctrl |= 0x8;
@@ -356,117 +364,6 @@ static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
 }
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC)
-static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci)
-{
-	u16 misc_ctrl;
-	u32 vendor_ctrl;
-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
-	struct sdhci_tegra *tegra_host = pltfm_host->priv;
-	const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
-
-	if (tegra_host->sd_stat_head != NULL) {
-		tegra_host->sd_stat_head->data_crc_count = 0;
-		tegra_host->sd_stat_head->cmd_crc_count = 0;
-		tegra_host->sd_stat_head->data_to_count = 0;
-		tegra_host->sd_stat_head->cmd_to_count = 0;
-	}
-	/* Set the base clock frequency */
-	vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
-	vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
-	vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) <<
-		SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
-	vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
-	vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE;
-
-	/* Set tap delay */
-	if (plat->tap_delay) {
-		vendor_ctrl &= ~(0xFF <<
-			SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-		vendor_ctrl |= (plat->tap_delay <<
-			SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-	}
-	/* Enable frequency tuning for SDR50 mode */
-	vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDR50_TUNING;
-	sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
-
-	/* Enable SDHOST v3.0 support */
-	misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
-	misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_SD_3_0 |
-		SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT |
-		SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT;
-	sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
-}
-#endif
-
-#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
-static void tegra11x_sdhci_post_reset_init(struct sdhci_host *sdhci)
-{
-	u16 misc_ctrl;
-	u32 vendor_ctrl;
-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
-	struct sdhci_tegra *tegra_host = pltfm_host->priv;
-	struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
-	struct tegra_sdhci_platform_data *plat;
-
-	if (tegra_host->sd_stat_head != NULL) {
-		tegra_host->sd_stat_head->data_crc_count = 0;
-		tegra_host->sd_stat_head->cmd_crc_count = 0;
-		tegra_host->sd_stat_head->data_to_count = 0;
-		tegra_host->sd_stat_head->cmd_to_count = 0;
-	}
-
-	plat = pdev->dev.platform_data;
-	/* Set the base clock frequency */
-	vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
-	vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT);
-	vendor_ctrl |= (tegra11_sdhost_max_clk[tegra_host->instance] / 1000000)
-			<< SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT;
-	vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE;
-	vendor_ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE;
-
-	/*
-	 * Set tap delay
-	 * If tuning is already done and the card is powered ON across
-	 * suspend, then program the tap value obtained through tuning
-	 * as only the controller context is restored. In other cases, set
-	 * the default tap delay value.
-	 */
-	if ((tegra_host->tuning_status == TUNING_STATUS_DONE) &&
-		(sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
-			vendor_ctrl &= ~(0xFF <<
-				SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-			vendor_ctrl |=
-				(tegra_host->tuning_data.best_tap_value <<
-				SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-	} else {
-		if (plat->tap_delay) {
-			vendor_ctrl &= ~(0xFF <<
-				SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-			vendor_ctrl |= (plat->tap_delay <<
-				SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-		}
-	}
-
-	/* Set trim delay */
-	vendor_ctrl &= ~(0x1F <<
-		SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT);
-	vendor_ctrl |= (plat->trim_delay <<
-		SDHCI_VENDOR_CLOCK_CNTRL_TRIM_VALUE_SHIFT);
-	sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
-
-	/* Enable SDHOST v3.0 support */
-	misc_ctrl = sdhci_readw(sdhci, SDHCI_VENDOR_MISC_CNTRL);
-	misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR104_SUPPORT |
-		SDHCI_VENDOR_MISC_CNTRL_ENABLE_SDR50_SUPPORT;
-	/* Enable DDR mode support only for SDMMC4 */
-	if (tegra_host->instance == 3)
-		misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_ENABLE_DDR50_SUPPORT;
-	misc_ctrl |= SDHCI_VENDOR_MISC_CNTRL_INFINITE_ERASE_TIMEOUT;
-	sdhci_writew(sdhci, misc_ctrl, SDHCI_VENDOR_MISC_CNTRL);
-}
-#endif
-
 static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 		unsigned int uhs)
 {
@@ -510,13 +407,81 @@ static int tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 
 static void tegra_sdhci_reset_exit(struct sdhci_host *sdhci, u8 mask)
 {
+	u16 misc_ctrl;
+	u32 vendor_ctrl;
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
 	struct sdhci_tegra *tegra_host = pltfm_host->priv;
 	const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
+	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
 
 	if (mask & SDHCI_RESET_ALL) {
-		if (tegra_host->hw_ops->sdhost_init)
-			tegra_host->hw_ops->sdhost_init(sdhci);
+		if (tegra_host->sd_stat_head != NULL) {
+			tegra_host->sd_stat_head->data_crc_count = 0;
+			tegra_host->sd_stat_head->cmd_crc_count = 0;
+			tegra_host->sd_stat_head->data_to_count = 0;
+			tegra_host->sd_stat_head->cmd_to_count = 0;
+		}
+		vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
+		if (soc_data->nvquirks & NVQUIRK_ENABLE_PADPIPE_CLKEN) {
+			vendor_ctrl |=
+				SDHCI_VNDR_CLK_CTRL_PADPIPE_CLKEN_OVERRIDE;
+		}
+		if (soc_data->nvquirks & NVQUIRK_DISABLE_SPI_MODE_CLKEN) {
+			vendor_ctrl &=
+				~SDHCI_VNDR_CLK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
+		}
+		if (soc_data->nvquirks & NVQUIRK_SET_TAP_DELAY) {
+			if ((tegra_host->tuning_status == TUNING_STATUS_DONE) &&
+				(sdhci->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
+					vendor_ctrl &= ~(0xFF <<
+					SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
+					vendor_ctrl |=
+					(tegra_host->tuning_data.best_tap_value
+					<< SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
+			} else {
+				if (plat->tap_delay) {
+					vendor_ctrl &= ~(0xFF <<
+					SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
+					vendor_ctrl |= (plat->tap_delay <<
+					SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
+				}
+			}
+		}
+		if (soc_data->nvquirks & NVQUIRK_SET_TRIM_DELAY) {
+			if (plat->trim_delay) {
+				vendor_ctrl &= ~(0x1F <<
+				SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
+				vendor_ctrl |= (plat->trim_delay <<
+				SDHCI_VNDR_CLK_CTRL_TRIM_VALUE_SHIFT);
+			}
+		}
+		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50_TUNING)
+			vendor_ctrl |= SDHCI_VNDR_CLK_CTRL_SDR50_TUNING;
+		sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
+
+		misc_ctrl = sdhci_readw(sdhci, SDHCI_VNDR_MISC_CTRL);
+		if (soc_data->nvquirks & NVQUIRK_ENABLE_SD_3_0)
+			misc_ctrl |= SDHCI_VNDR_MISC_CTRL_ENABLE_SD_3_0;
+		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) {
+			misc_ctrl |=
+			SDHCI_VNDR_MISC_CTRL_ENABLE_SDR104_SUPPORT;
+		}
+		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) {
+			misc_ctrl |=
+			SDHCI_VNDR_MISC_CTRL_ENABLE_SDR50_SUPPORT;
+		}
+		/* Enable DDR mode support only for SDMMC4 */
+		if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) {
+			if (tegra_host->instance == 3) {
+				misc_ctrl |=
+				SDHCI_VNDR_MISC_CTRL_ENABLE_DDR50_SUPPORT;
+			}
+		}
+		if (soc_data->nvquirks & NVQUIRK_INFINITE_ERASE_TIMEOUT) {
+			misc_ctrl |=
+			SDHCI_VNDR_MISC_CTRL_INFINITE_ERASE_TIMEOUT;
+		}
+		sdhci_writew(sdhci, misc_ctrl, SDHCI_VNDR_MISC_CTRL);
 
 		/* Mask the support for any UHS modes if specified */
 		if (plat->uhs_mask & MMC_UHS_MASK_SDR104)
@@ -864,9 +829,9 @@ static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
 		if (!tegra_host->clk_enabled) {
 			pm_runtime_get_sync(&pdev->dev);
 			clk_prepare_enable(pltfm_host->clk);
-			ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
-			ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
-			sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
+			ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
+			ctrl |= SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
+			sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
 			tegra_host->clk_enabled = true;
 		}
 		tegra_sdhci_set_clk_rate(sdhci, clock);
@@ -875,9 +840,9 @@ static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock)
 	} else if (!clock && tegra_host->clk_enabled) {
 		if (tegra_host->hw_ops->set_card_clock)
 			tegra_host->hw_ops->set_card_clock(sdhci, clock);
-		ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
-		ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_SDMMC_CLK;
-		sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
+		ctrl = sdhci_readb(sdhci, SDHCI_VNDR_CLK_CTRL);
+		ctrl &= ~SDHCI_VNDR_CLK_CTRL_SDMMC_CLK;
+		sdhci_writeb(sdhci, ctrl, SDHCI_VNDR_CLK_CTRL);
 		clk_disable_unprepare(pltfm_host->clk);
 		pm_runtime_put_sync(&pdev->dev);
 		tegra_host->clk_enabled = false;
@@ -908,10 +873,6 @@ static void tegra_sdhci_do_calibration(struct sdhci_host *sdhci)
 	if (tegra_host->instance == 3)
 		return;
 
-	/*
-	 * Do not enable auto calibration if the platform doesn't
-	 * support it.
-	 */
 	if (unlikely(soc_data->nvquirks & NVQUIRK_DISABLE_AUTO_CALIBRATION))
 		return;
 
@@ -1081,10 +1042,10 @@ static void sdhci_tegra_set_tap_delay(struct sdhci_host *sdhci,
 	/* Max tap delay value is 255 */
 	BUG_ON(tap_delay > MAX_TAP_VALUES);
 
-	vendor_ctrl = sdhci_readl(sdhci, SDHCI_VENDOR_CLOCK_CNTRL);
-	vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-	vendor_ctrl |= (tap_delay << SDHCI_VENDOR_CLOCK_CNTRL_TAP_VALUE_SHIFT);
-	sdhci_writel(sdhci, vendor_ctrl, SDHCI_VENDOR_CLOCK_CNTRL);
+	vendor_ctrl = sdhci_readl(sdhci, SDHCI_VNDR_CLK_CTRL);
+	vendor_ctrl &= ~(0xFF << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
+	vendor_ctrl |= (tap_delay << SDHCI_VNDR_CLK_CTRL_TAP_VALUE_SHIFT);
+	sdhci_writel(sdhci, vendor_ctrl, SDHCI_VNDR_CLK_CTRL);
 }
 
 static int sdhci_tegra_sd_error_stats(struct sdhci_host *host, u32 int_status)
@@ -1768,12 +1729,26 @@ static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
 static struct sdhci_tegra_soc_data soc_data_tegra20 = {
 	.pdata = &sdhci_tegra20_pdata,
 	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
+		   NVQUIRK_ENABLE_PADPIPE_CLKEN |
+		   NVQUIRK_DISABLE_SPI_MODE_CLKEN |
+		   NVQUIRK_SET_TAP_DELAY |
+		   NVQUIRK_ENABLE_SDR50_TUNING |
+		   NVQUIRK_ENABLE_SDR50 |
+		   NVQUIRK_ENABLE_SDR104 |
+#endif
 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
 		    NVQUIRK_SET_DRIVE_STRENGTH |
-#elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
+#endif
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
 		    NVQUIRK_DISABLE_AUTO_CALIBRATION |
 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
 		    NVQUIRK_SET_CALIBRATION_OFFSETS |
+		    NVQUIRK_ENABLE_SD_3_0 |
+#else
+		    NVQUIRK_SET_TRIM_DELAY |
+		    NVQUIRK_ENABLE_DDR50 |
+		    NVQUIRK_INFINITE_ERASE_TIMEOUT |
 #endif
 		    NVQUIRK_ENABLE_BLOCK_GAP_DET,
 };