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authorRichard Zhu <r65037@freescale.com>2011-01-05 14:16:21 +0800
committerAlan Tull <alan.tull@freescale.com>2011-02-03 16:36:05 -0600
commitb4711f2599cf5cc246af91a4b8d88f345ab8428c (patch)
treebc881335aeb57c11f1d8e6fb5f01684dba49d61e /drivers/mmc
parent2b4ea702e7964f2556150c8f56508c4f5425381f (diff)
ENGR00137502-2 SDHCI: Enable Sandisk eMMC DDR mode on SMD
A while delay is mandatory required by Sandisk eMMC44 card when enable the DDR mode, since this eMMC44 chip soldered on the SMD board is not abide to the eMMC spec. Signed-off-by: Richard Zhu <r65037@freescale.com>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/mx_sdhci.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/mmc/host/mx_sdhci.c b/drivers/mmc/host/mx_sdhci.c
index b7f08d80610d..54910b72d6b0 100644
--- a/drivers/mmc/host/mx_sdhci.c
+++ b/drivers/mmc/host/mx_sdhci.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -802,6 +802,12 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
/* Configure the cmd type for cmd12 */
if (cmd->opcode == 12)
mode |= SDHCI_TRNS_ABORTCMD;
+ /*
+ * Some delay is mandatory required between CMD6 and CMD13 after
+ * switch to DDR mode when Sandisk eMMC44 soldered on SMD board
+ */
+ if (cmd->opcode == 0xd)
+ mdelay(5);
DBG("Complete sending cmd, transfer mode would be 0x%x.\n", mode);
writel(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
}