ENGR00169906-4 MXS-DMA : change the last parameter of mxs_dma_prep_slave_sg()

For a long DMA chain which may have more then two DMA Command Structures,
the current DMA code sets the WAIT4END bit at the last one, such as:

+-----+		      +-----+			   +-----+
| cmd | ------------> | cmd | ------------------>  | cmd |
+-----+		      +-----+			   +-----+
						       ^
						       |
						       |
						      set WAIT4END here

But in the NAND ECC read case, the WAIT4END bit should be set
not only at the last DMA Command Structure, but also at the middle one,
such as:

+-----+		      +-----+			   +-----+
| cmd | ------------> | cmd | ------------------>  | cmd |
+-----+		      +-----+			   +-----+
                         ^                            ^
			 |                            |
			 |                            |
			set WAIT4END here too        set WAIT4END here

We set the WAIT4END in the middle DMA Command Structure to ensure
the BCH module finishs its job. If we do not wait in this situation,
the BCH module may be changed in the following DMA Command Structures,
and it maybe becomes unstable which will cause a DMA timeout
This has been catched in the MX6Q board.

So rewrite the last parameter of mxs_dma_prep_slave_sg().
Add some more flags to let the driver sets the WAIT4END as it needs.

Acked-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>

0 files changed, 0 insertions, 0 deletions