diff options
| author | Han Xu <han.xu@nxp.com> | 2018-06-22 11:31:48 -0500 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:33:12 +0800 |
| commit | 074c0daeca0ad21ea32e75e29e05f7d4d7a64bb0 (patch) | |
| tree | ffcea81e57eec9c5f2d949465b62eff72910c365 /drivers/mtd | |
| parent | b0e1908122defe9c1059aac23c9ca42db416fb16 (diff) | |
MLK-18669-2: mtd: flexspi: enable Quad DDR read for i.MX8MM FlexSPI Nor
i.MX8MM MEK only supports Quad mode for flexspi nor, enable the quad ddr
mode for better performance.
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit a0abea8ca8d493fc2861c84f1475c0eb388899ce)
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-flexspi.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/mtd/spi-nor/fsl-flexspi.c b/drivers/mtd/spi-nor/fsl-flexspi.c index a5523eb830e2..a63650649350 100644 --- a/drivers/mtd/spi-nor/fsl-flexspi.c +++ b/drivers/mtd/spi-nor/fsl-flexspi.c @@ -32,6 +32,9 @@ #include <soc/imx8/sc/sci.h> #include <linux/pm_runtime.h> +/* Board only enabled up to Quad mode, not Octal*/ +#define FLEXSPI_QUIRK_QUAD_ONLY (1 << 0) + /* runtime pm timeout */ #define FSL_FLEXSPI_RPM_TIMEOUT 50 /* 50ms */ @@ -442,7 +445,7 @@ static struct fsl_flexspi_devtype_data imx8mm_data = { .rxfifo = 1024, .txfifo = 1024, .ahb_buf_size = 2048, - .driver_data = 0, + .driver_data = FLEXSPI_QUIRK_QUAD_ONLY, }; #define FSL_FLEXSPI_MAX_CHIP 4 @@ -468,6 +471,11 @@ struct fsl_flexspi { struct pm_qos_request pm_qos_req; }; +static inline int fsl_flexspi_quad_only(struct fsl_flexspi *flex) +{ + return flex->devtype_data->driver_data & FLEXSPI_QUIRK_QUAD_ONLY; +} + static inline void fsl_flexspi_unlock_lut(struct fsl_flexspi *flex) { writel(FLEXSPI_LUTKEY_VALUE, flex->iobase + FLEXSPI_LUTKEY); @@ -556,11 +564,11 @@ static void fsl_flexspi_init_lut(struct fsl_flexspi *flex) /* DDR Quad Fast Read */ } else if (op == SPINOR_OP_READ_1_1_4_D) { /* read mode : 1-1-4, such as Micron N25Q256A. */ - writel(LUT0(CMD_DDR, PAD1, op) | + writel(LUT0(CMD, PAD1, op) | LUT1(ADDR_DDR, PAD1, addrlen), base + FLEXSPI_LUT(lut_base)); - writel(LUT0(DUMMY, PAD1, dm) | + writel(LUT0(DUMMY_DDR, PAD4, dm * 2) | LUT1(READ_DDR, PAD4, 0), base + FLEXSPI_LUT(lut_base + 1)); @@ -1302,7 +1310,8 @@ static int fsl_flexspi_probe(struct platform_device *pdev) ret = of_property_read_u32(np, "spi-nor,ddr-quad-read-dummy", &dummy); if (!ret && dummy > 0) - hwcaps.mask |= SNOR_HWCAPS_READ; + hwcaps.mask |= fsl_flexspi_quad_only(flex) ? + SNOR_HWCAPS_READ_1_1_4 :SNOR_HWCAPS_READ_1_8_8; else hwcaps.mask |= SNOR_HWCAPS_READ; |