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authorHan Xu <han.xu@nxp.com>2018-09-28 10:40:09 -0500
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:34:18 +0800
commit77ce81accab5e155451afdb5a188c41f9a36dc10 (patch)
treead8660cb0712cb01ee3394adca318adbf568375b /drivers/mtd
parent21d24d51ea2f6d51e5023d5020662c930dcf2fcb (diff)
MLK-18997: mtd: fsl-quadspi: disable the TDH DDR enable bit if it's been set
for 6UL/7D, the TDH bit should only be set when DDR mode enabled. This bit cannot be cleared during module reset, so check this bit in nor_setup to make sure it cleard and won't affect the following operations. Signed-off-by: Han Xu <han.xu@nxp.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/spi-nor/fsl-quadspi.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index acffb34e2c04..a2360558a26b 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -821,6 +821,10 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
| QUADSPI_SMPR_HSENA_MASK
| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
+ /* disable the TDH bit of FLSHCR if it's been set*/
+ reg = qspi_readl(q, base + QUADSPI_FLSHCR);
+ qspi_writel(q, reg & ~QUADSPI_FLSHCR_TDH_MASK, base + QUADSPI_FLSHCR);
+
/* Enable the module */
qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
base + QUADSPI_MCR);