ENGR00118544 iMX23 Clear dangerous macro stmp3xxx_setl(clearl)

No all regiser use _SCT. stmp3xxx_setl may write to wrong address.
please use __raw_write (value, REG_XXX_SET) to write date to SCT
register.  Only REG_XXX_SCT is defined when it exist at hardware.

Signed-off-by: Frank.Li <Frank.Li@freescale.com>

4 files changed, 35 insertions, 29 deletions

diff --git a/drivers/mtd/nand/gpmi/gpmi-base.c b/drivers/mtd/nand/gpmi/gpmi-base.c
index e10a175f3d4d..d2c10cc94320 100644
--- a/drivers/mtd/nand/gpmi/gpmi-base.c
+++ b/drivers/mtd/nand/gpmi/gpmi-base.c
@@ -249,8 +249,8 @@ static void gpmi_timer_expiry(unsigned long d)
 		g->timer.expires = jiffies + 4 * HZ;
 		add_timer(&g->timer);
 	} else {
-		stmp3xxx_setl(BM_GPMI_CTRL0_CLKGATE,
-			      REGS_GPMI_BASE + HW_GPMI_CTRL0);
+		__raw_writel(BM_GPMI_CTRL0_CLKGATE,
+			      REGS_GPMI_BASE + HW_GPMI_CTRL0_SET);
 		clk_disable(g->clk);
 		g->self_suspended = 1;
 	}
@@ -265,7 +265,7 @@ static void gpmi_self_wakeup(struct gpmi_nand_data *g)
 #ifdef CONFIG_PM
 	int i = 1000;
 	clk_enable(g->clk);
-	stmp3xxx_clearl(BM_GPMI_CTRL0_CLKGATE, REGS_GPMI_BASE + HW_GPMI_CTRL0);
+	__raw_writel(BM_GPMI_CTRL0_CLKGATE, REGS_GPMI_BASE + HW_GPMI_CTRL0_CLR);
 	while (i--
 	       && __raw_readl(REGS_GPMI_BASE +
 			      HW_GPMI_CTRL0) & BM_GPMI_CTRL0_CLKGATE) ;
@@ -344,9 +344,9 @@ void gpmi_set_timings(struct gpmi_nand_data *g,
 
 	/* Reset the DLL and sample delay to known values. */
 
-	stmp3xxx_clearl(
+	__raw_writel(
 		BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_DLL_ENABLE,
-					REGS_GPMI_BASE + HW_GPMI_CTRL1);
+					REGS_GPMI_BASE + HW_GPMI_CTRL1_CLR);
 
 	/*
 	 * Check how fast the GPMI clock is running. If it's running very
@@ -718,7 +718,8 @@ set_up_the_hardware:
 	 */
 
 	/* BW_GPMI_CTRL1_DLL_ENABLE(0); */
-	stmp3xxx_clearl(BM_GPMI_CTRL1_DLL_ENABLE, REGS_GPMI_BASE+HW_GPMI_CTRL1);
+	__raw_writel(BM_GPMI_CTRL1_DLL_ENABLE,
+		REGS_GPMI_BASE+HW_GPMI_CTRL1_CLR);
 
 	if ((data_sample_delay_in_cycles == 0) ||
 			(gpmi_clock_period_in_ns > GPMI_MAX_DLL_PERIOD_NS)) {
@@ -729,11 +730,11 @@ set_up_the_hardware:
 		 */
 
 		/* BW_GPMI_CTRL1_RDN_DELAY(0); */
-		stmp3xxx_clearl(BM_GPMI_CTRL1_RDN_DELAY,
-						REGS_GPMI_BASE + HW_GPMI_CTRL1);
+		__raw_writel(BM_GPMI_CTRL1_RDN_DELAY,
+				REGS_GPMI_BASE + HW_GPMI_CTRL1_CLR);
 		/* BW_GPMI_CTRL1_HALF_PERIOD(0); */
-		stmp3xxx_clearl(BM_GPMI_CTRL1_HALF_PERIOD,
-						REGS_GPMI_BASE + HW_GPMI_CTRL1);
+		__raw_writel(BM_GPMI_CTRL1_HALF_PERIOD,
+				REGS_GPMI_BASE + HW_GPMI_CTRL1_CLR);
 
 	} else {
 
@@ -751,8 +752,8 @@ set_up_the_hardware:
 		__raw_writel(register_image, REGS_GPMI_BASE + HW_GPMI_CTRL1);
 
 		/* BW_GPMI_CTRL1_DLL_ENABLE(1); */
-		stmp3xxx_setl(BM_GPMI_CTRL1_DLL_ENABLE,
-						REGS_GPMI_BASE + HW_GPMI_CTRL1);
+		__raw_writel(BM_GPMI_CTRL1_DLL_ENABLE,
+			REGS_GPMI_BASE + HW_GPMI_CTRL1_SET);
 
 		/*
 		 * After we enable the GPMI DLL, we have to wait
@@ -859,21 +860,22 @@ static int gpmi_nand_init_hw(struct platform_device *pdev, int request_pins)
 	stmp3xxx_reset_block(HW_GPMI_CTRL0 + REGS_GPMI_BASE, 1);
 
 	/* this CLEARS reset, despite of its name */
-	stmp3xxx_setl(BM_GPMI_CTRL1_DEV_RESET, REGS_GPMI_BASE + HW_GPMI_CTRL1);
+	__raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+		REGS_GPMI_BASE + HW_GPMI_CTRL1_SET);
 
 	/* IRQ polarity */
-	stmp3xxx_setl(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
-		      REGS_GPMI_BASE + HW_GPMI_CTRL1);
+	__raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+		      REGS_GPMI_BASE + HW_GPMI_CTRL1_SET);
 
 	/*
 	 * Select the ECC to use. The bch_mode() function returns a value that
 	 * selects whichever hardware is appropriate (q.v.).
 	 */
-	stmp3xxx_setl(bch_mode(), REGS_GPMI_BASE + HW_GPMI_CTRL1);
+	__raw_writel(bch_mode(), REGS_GPMI_BASE + HW_GPMI_CTRL1_SET);
 
 	/* Choose NAND mode (1 means ATA, 0 - NAND */
-	stmp3xxx_clearl(BM_GPMI_CTRL1_GPMI_MODE,
-			REGS_GPMI_BASE + HW_GPMI_CTRL1);
+	__raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+			REGS_GPMI_BASE + HW_GPMI_CTRL1_CLR);
 
 out:
 	return err;
@@ -892,7 +894,7 @@ static void gpmi_nand_release_hw(struct platform_device *pdev)
 	struct gpmi_platform_data *gpd =
 	    (struct gpmi_platform_data *)pdev->dev.platform_data;
 
-	stmp3xxx_setl(BM_GPMI_CTRL0_SFTRST, REGS_GPMI_BASE + HW_GPMI_CTRL0);
+	__raw_writel(BM_GPMI_CTRL0_SFTRST, REGS_GPMI_BASE + HW_GPMI_CTRL0_SET);
 
 	clk_disable(g->clk);
 	clk_put(g->clk);
@@ -1735,8 +1737,8 @@ static irqreturn_t gpmi_irq(int irq, void *context)
 		stmp3xxx_dma_clear_interrupt(g->cchip->dma_ch);
 		complete(&g->done);
 	}
-	stmp3xxx_clearl(BM_GPMI_CTRL1_DEV_IRQ | BM_GPMI_CTRL1_TIMEOUT_IRQ,
-			REGS_GPMI_BASE + HW_GPMI_CTRL1);
+	__raw_writel(BM_GPMI_CTRL1_DEV_IRQ | BM_GPMI_CTRL1_TIMEOUT_IRQ,
+			REGS_GPMI_BASE + HW_GPMI_CTRL1_CLR);
 	return IRQ_HANDLED;
 }
 
diff --git a/drivers/mtd/nand/gpmi/gpmi-bch.c b/drivers/mtd/nand/gpmi/gpmi-bch.c
index 47c409f9d0ec..b4555817a622 100644
--- a/drivers/mtd/nand/gpmi/gpmi-bch.c
+++ b/drivers/mtd/nand/gpmi/gpmi-bch.c
@@ -93,7 +93,8 @@ static struct bch_state_t state = {
 static int bch_reset(void *context, int index)
 {
 	stmp3xxx_reset_block(REGS_BCH_BASE, true);
-	stmp3xxx_setl(BM_BCH_CTRL_COMPLETE_IRQ_EN, REGS_BCH_BASE + HW_BCH_CTRL);
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+		REGS_BCH_BASE + HW_BCH_CTRL_SET);
 	return 0;
 }
 
@@ -148,7 +149,7 @@ static irqreturn_t bch_irq(int irq, void *context)
 	if (s0 & BM_BCH_STATUS0_UNCORRECTABLE)
 		stat.failed++;
 
-	stmp3xxx_clearl(BM_BCH_CTRL_COMPLETE_IRQ, REGS_BCH_BASE + HW_BCH_CTRL);
+	__raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, REGS_BCH_BASE + HW_BCH_CTRL_CLR);
 
 	pr_debug("%s: chip %d, failed %d, corrected %d\n",
 			__func__, r,
diff --git a/drivers/mtd/nand/gpmi/gpmi-ecc8.c b/drivers/mtd/nand/gpmi/gpmi-ecc8.c
index d1b30c088328..5c7f27840f47 100644
--- a/drivers/mtd/nand/gpmi/gpmi-ecc8.c
+++ b/drivers/mtd/nand/gpmi/gpmi-ecc8.c
@@ -118,8 +118,10 @@ static int  ecc8_reset(void *context, int index)
 {
 	stmp3xxx_reset_block(REGS_ECC8_BASE, false);
 	while (__raw_readl(REGS_ECC8_BASE + HW_ECC8_CTRL) & BM_ECC8_CTRL_AHBM_SFTRST)
-		stmp3xxx_clearl(BM_ECC8_CTRL_AHBM_SFTRST, REGS_ECC8_BASE + HW_ECC8_CTRL);
-	stmp3xxx_setl(BM_ECC8_CTRL_COMPLETE_IRQ_EN, REGS_ECC8_BASE + HW_ECC8_CTRL);
+		__raw_writel(BM_ECC8_CTRL_AHBM_SFTRST,
+			REGS_ECC8_BASE + HW_ECC8_CTRL_CLR);
+	__raw_writel(BM_ECC8_CTRL_COMPLETE_IRQ_EN,
+			REGS_ECC8_BASE + HW_ECC8_CTRL_SET);
 	return 0;
 }
 
@@ -205,7 +207,8 @@ static irqreturn_t ecc8_irq(int irq, void *context)
 
 	complete(&state->done);
 
-	stmp3xxx_clearl(BM_ECC8_CTRL_COMPLETE_IRQ, REGS_ECC8_BASE + HW_ECC8_CTRL);
+	__raw_writel(BM_ECC8_CTRL_COMPLETE_IRQ,
+		REGS_ECC8_BASE + HW_ECC8_CTRL_CLR);
 	return IRQ_HANDLED;
 }
 
diff --git a/drivers/mtd/nand/lba/gpmi-transport.c b/drivers/mtd/nand/lba/gpmi-transport.c
index 0073842db6b9..f3eecc06f653 100644
--- a/drivers/mtd/nand/lba/gpmi-transport.c
+++ b/drivers/mtd/nand/lba/gpmi-transport.c
@@ -73,8 +73,8 @@ static irqreturn_t gpmi_irq(int irq, void *context)
 		}
 
 	}
-	stmp3xxx_clearl(BM_GPMI_CTRL1_DEV_IRQ | BM_GPMI_CTRL1_TIMEOUT_IRQ,
-			REGS_GPMI_BASE + HW_GPMI_CTRL1);
+	__raw_writel(BM_GPMI_CTRL1_DEV_IRQ | BM_GPMI_CTRL1_TIMEOUT_IRQ,
+			REGS_GPMI_BASE + HW_GPMI_CTRL1_CLR);
 	return IRQ_HANDLED;
 }
 
@@ -165,7 +165,7 @@ void queue_plug(struct lba_data *data)
 
 void queue_release(struct lba_data *data)
 {
-	stmp3xxx_setl(BM_GPMI_CTRL0_SFTRST, REGS_GPMI_BASE + HW_GPMI_CTRL0);
+	__raw_writel(BM_GPMI_CTRL0_SFTRST, REGS_GPMI_BASE + HW_GPMI_CTRL0_SET);
 
 	clk_disable(data->clk);
 }