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authorHan Xu <b45815@freescale.com>2015-06-10 17:14:01 -0500
committerNitin Garg <nitin.garg@nxp.com>2016-01-14 11:02:38 -0600
commit8308b1df9013546b47073fb3088237f55f03d88b (patch)
tree5ad45edaf7bef272bb41a688bfb7b7c72526f854 /drivers/mtd
parent3789ec9f5fcd96cf87a186c219a55d62e9694ecd (diff)
MLK-11087: mtd:qspi: support DDR Quad mode for Macronix mx25l51245g
Enable DDR quad mode for Macronix qspi chip mx25l51245g by setting Quad bit in status register and enabling in dts file. The LUT for SPINOR_OP_READ_1_4_4_D was initially designed for Spansion qspi chip, so there is one cycle for "mode" after address and before dummy. While Macronix qspi chip doesn't have this feature, so we just take off one cycle in dts file to bypass this problem. Signed-off-by: Han Xu <b45815@freescale.com> (cherry picked and merge from commit e03fdad1c7713a7db70112e00c4ae96848accd34)
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/spi-nor/spi-nor.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index bce6fa20f8f3..e8b977c886f6 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -978,6 +978,14 @@ static int set_ddr_quad_mode(struct spi_nor *nor, struct flash_info *info)
return status;
}
return status;
+ case CFI_MFR_MACRONIX:
+ status = macronix_quad_enable(nor);
+ if (status) {
+ dev_err(nor->dev,
+ "Macronix DDR quad-read not enabled\n");
+ return status;
+ }
+ return status;
case CFI_MFR_ST: /* Micron, actually */
/* DTR quad read works with the Extended SPI protocol. */
return 0;
@@ -1181,6 +1189,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
} else if (JEDEC_MFR(info) == CFI_MFR_ST) {
nor->read_opcode = SPINOR_OP_READ_1_1_4_D;
+ } else if (JEDEC_MFR(info) == CFI_MFR_MACRONIX) {
+ nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
} else {
dev_err(dev, "DDR Quad Read is not supported.\n");
return -EINVAL;