diff options
| author | Han Xu <han.xu@nxp.com> | 2017-06-05 16:19:39 -0500 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 926ef66fb54ce931949a7e3a2e7b5c0a7aee57f9 (patch) | |
| tree | bd6a568d44ab30b6e8b01ef6782fdc2c08f0362f /drivers/mtd | |
| parent | a3070cdcc4df33e176e191da967342c80d9fcdd4 (diff) | |
MLK-15052-3: mtd: spi-nor: enable octal read mode in spi framework
Enhanced spi-nor framework to support octal read mode
Signed-off-by: Han Xu <han.xu@nxp.com>
Acked-by: Frank Li <frank.li@nxp.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 0b6134f48d66..76087e80ceb0 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -77,6 +77,7 @@ struct flash_info { * SPI_NOR_HAS_LOCK. */ #define SPI_NOR_DDR_QUAD_READ BIT(10) /* Flash supports DDR Quad Read */ +#define SPI_NOR_DDR_OCTAL_READ BIT(11) /* Flash supports DDR Octal Read */ }; #define JEDEC_MFR(info) ((info)->id[0]) @@ -149,6 +150,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) { switch (nor->flash_read) { case SPI_NOR_DDR_QUAD: + case SPI_NOR_DDR_OCTAL: { struct device_node *np = spi_nor_get_flash_node(nor); u32 dummy; @@ -161,11 +163,13 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) */ if (!of_property_read_u32(np, "spi-nor,ddr-quad-read-dummy", &dummy)) + pr_err("DUMMY CYCLE : %d !!!\n", dummy); return dummy; } case SPI_NOR_FAST: case SPI_NOR_DUAL: case SPI_NOR_QUAD: + case SPI_NOR_OCTAL: return 8; case SPI_NOR_NORMAL: return 0; @@ -907,6 +911,7 @@ static const struct flash_info spi_nor_ids[] = { { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + {"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | SPI_NOR_DDR_OCTAL_READ) }, /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, @@ -1486,8 +1491,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (info->flags & SPI_NOR_NO_FR) nor->flash_read = SPI_NOR_NORMAL; - /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */ - if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) { + /* DDR Octal/Quad/Dual-read mode takes precedence over fast/normal */ + if (mode == SPI_NOR_DDR_OCTAL && info->flags & SPI_NOR_DDR_OCTAL_READ) { + nor->flash_read = SPI_NOR_DDR_OCTAL; + } else if (mode == SPI_NOR_DDR_QUAD && + info->flags & SPI_NOR_DDR_QUAD_READ) { ret = set_ddr_quad_mode(nor, info); if (ret) { dev_err(dev, "DDR quad mode not supported\n"); @@ -1507,6 +1515,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) /* Default commands */ switch (nor->flash_read) { + case SPI_NOR_DDR_OCTAL: + nor->read_opcode = SPINOR_OP_READ_1_1_8_D; + break; case SPI_NOR_DDR_QUAD: if (JEDEC_MFR(info) == CFI_MFR_AMD) { /* Spansion */ nor->read_opcode = SPINOR_OP_READ_1_4_4_D; @@ -1546,6 +1557,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { /* Dedicated 4-byte command set */ switch (nor->flash_read) { + case SPI_NOR_DDR_OCTAL: + case SPI_NOR_OCTAL: + nor->read_opcode = SPINOR_OP_READ_1_1_8_D; + break; case SPI_NOR_DDR_QUAD: nor->read_opcode = SPINOR_OP_READ4_1_4_4_D; break; |