diff options
author | Even Xu <Feng.Xu@freescale.com> | 2011-11-28 14:29:32 +0800 |
---|---|---|
committer | Jason Liu <r64343@freescale.com> | 2012-01-09 21:08:26 +0800 |
commit | 9bc986dd627a55aca3f1f8f8ef3bec071e146650 (patch) | |
tree | bbd2cabe888732862397461b58fb5654af46fe66 /drivers/mxc/ipu3 | |
parent | 021b7b904db318335a85f3e650548d3c8894a866 (diff) |
ENGR00163247-2 MX6Q: MIPI sensor add prp viewfinder and prp enc support
1. Enable ipu channel mipi setting
2. Change mipi csi2 driver common API to use lock
Signed-off-by: Even Xu <b21019@freescale.com>
Diffstat (limited to 'drivers/mxc/ipu3')
-rw-r--r-- | drivers/mxc/ipu3/ipu_common.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index 68062616a1c3..e7713199abcb 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -688,9 +688,16 @@ int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel ipu->ic_use_count++; ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel; - /*Without SMFC, CSI only support parallel data source*/ - ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + - params->csi_prp_enc_mem.csi)); + if (params->csi_prp_enc_mem.mipi_en) { + ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_enc_mem.csi)); + _ipu_csi_set_mipi_di(ipu, + params->csi_prp_enc_mem.mipi_vc, + params->csi_prp_enc_mem.mipi_id, + params->csi_prp_enc_mem.csi); + } else + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_enc_mem.csi)); /*CSI0/1 feed into IC*/ ipu_conf &= ~IPU_CONF_IC_INPUT; @@ -721,9 +728,16 @@ int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel ipu->ic_use_count++; ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel; - /*Without SMFC, CSI only support parallel data source*/ - ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + - params->csi_prp_vf_mem.csi)); + if (params->csi_prp_vf_mem.mipi_en) { + ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_vf_mem.csi)); + _ipu_csi_set_mipi_di(ipu, + params->csi_prp_vf_mem.mipi_vc, + params->csi_prp_vf_mem.mipi_id, + params->csi_prp_vf_mem.csi); + } else + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_vf_mem.csi)); /*CSI0/1 feed into IC*/ ipu_conf &= ~IPU_CONF_IC_INPUT; |