diff options
| author | Zhou Peng <eagle.zhou@nxp.com> | 2018-07-23 13:15:27 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 09e322d07bbcd6e76d6b2c01adfaf5c104596b9e (patch) | |
| tree | 484b0eec03ef0ec8d21554350fdb3d6f641e8845 /drivers/mxc | |
| parent | ed85de28304caca344c1cb53f83b907cd93e55b9 (diff) | |
MLK-19005 - [i.MX8MM/Hantro]: Conformace test failed when decoder and encoder run simultaneously
Add assert operaiton in reset functions, include g1/g2/h1
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Diffstat (limited to 'drivers/mxc')
| -rwxr-xr-x | drivers/mxc/hantro_845/hantrodec_845s.c | 18 | ||||
| -rwxr-xr-x | drivers/mxc/hantro_845_h1/hx280enc.c | 7 |
2 files changed, 22 insertions, 3 deletions
diff --git a/drivers/mxc/hantro_845/hantrodec_845s.c b/drivers/mxc/hantro_845/hantrodec_845s.c index 90649439d15e..9b7410fb1c3c 100755 --- a/drivers/mxc/hantro_845/hantrodec_845s.c +++ b/drivers/mxc/hantro_845/hantrodec_845s.c @@ -1,7 +1,7 @@ /***************************************************************************** * The GPL License (GPL) * - * Copyright (c) 2015-2017, VeriSilicon Inc. + * Copyright (c) 2015-2018, VeriSilicon Inc. * Copyright (c) 2011-2014, Google Inc. * * This program is free software; you can redistribute it and/or @@ -49,6 +49,8 @@ #include <linux/clk.h> #include <linux/busfreq-imx.h> +#include <linux/delay.h> + #ifdef CONFIG_DEVICE_THERMAL_XXX #include <linux/device_cooling.h> #define HANTRO_REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a) @@ -265,8 +267,13 @@ static int hantro_ctrlblk_reset(hantrodec_t *dev) iobase = (volatile u8 *)ioremap_nocache(BLK_CTL_BASE, 0x10000); if (dev->core_id == 0) { val = ioread32(iobase); + val &= (~0x2); + iowrite32(val, iobase); //assert G1 block soft reset control + udelay(2); + val = ioread32(iobase); val |= 0x2; - iowrite32(val, iobase); //VPUMIX G1 block soft reset control + iowrite32(val, iobase); //desert G1 block soft reset control + val = ioread32(iobase+4); val |= 0x2; iowrite32(val, iobase+4); //VPUMIX G1 block clock enable control @@ -274,8 +281,13 @@ static int hantro_ctrlblk_reset(hantrodec_t *dev) iowrite32(0xFFFFFFFF, iobase + 0xC); // all G1 fuse pp enable } else { val = ioread32(iobase); + val &= (~0x1); + iowrite32(val, iobase); //assert G2 block soft reset control + udelay(2); + val = ioread32(iobase); val |= 0x1; - iowrite32(val, iobase); //VPUMIX G2 block soft reset control + iowrite32(val, iobase); //desert G2 block soft reset control + val = ioread32(iobase+4); val |= 0x1; iowrite32(val, iobase+4); //VPUMIX G2 block clock enable control diff --git a/drivers/mxc/hantro_845_h1/hx280enc.c b/drivers/mxc/hantro_845_h1/hx280enc.c index fca529060535..6523d6cfac51 100755 --- a/drivers/mxc/hantro_845_h1/hx280enc.c +++ b/drivers/mxc/hantro_845_h1/hx280enc.c @@ -71,6 +71,8 @@ static struct clk *hantro_clk_h1_bus; #define IRQF_DISABLED 0x0 #endif +#include <linux/delay.h> + /* module description */ MODULE_LICENSE("GPL"); MODULE_AUTHOR("Google Finland Oy"); @@ -188,6 +190,11 @@ static int hantro_h1_ctrlblk_reset(struct device *dev) iobase = (volatile u8 *)ioremap_nocache(BLK_CTL_BASE, 0x10000); val = ioread32(iobase); + val &= (~0x4); + iowrite32(val, iobase); // assert soft reset + udelay(2); + + val = ioread32(iobase); val |= 0x4; iowrite32(val, iobase); // release soft reset |