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authorWayne Zou <b36644@freescale.com>2013-05-30 14:59:26 +0800
committerWayne Zou <b36644@freescale.com>2013-05-30 15:01:29 +0800
commitd9703615928db877ad6c23a807d0f80977891a32 (patch)
tree6e28accd47ed472ebb5d9cf38d7480abc1a6a4d7 /drivers/mxc
parentc42359044a3098c3a89eac9bb8990889cd90a0f7 (diff)
ENGR00264863 IPU: Fix interger overflow and check for invalid zero parameter
Fix interger overflow and check for invalid zero divider parameter Signed-off-by: Wayne Zou <b36644@freescale.com>
Diffstat (limited to 'drivers/mxc')
-rw-r--r--drivers/mxc/ipu3/ipu_disp.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c
index 35b78199b0df..87fa001b8246 100644
--- a/drivers/mxc/ipu3/ipu_disp.c
+++ b/drivers/mxc/ipu3/ipu_disp.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -61,7 +61,7 @@ static unsigned long _ipu_pixel_clk_get_rate(struct clk *clk)
{
struct ipu_soc *ipu = pixelclk2ipu(clk);
u32 div;
- u64 final_rate = clk_get_rate(clk->parent) * 16;
+ u64 final_rate = (unsigned long long)clk_get_rate(clk->parent) * 16;
_ipu_get(ipu);
div = ipu_di_read(ipu, clk->id, DI_BS_CLKGEN0);
@@ -1297,6 +1297,10 @@ int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
msleep(5);
/* Get integer portion of divider */
div = clk_get_rate(clk_get_parent(&ipu->pixel_clk[disp])) / rounded_pixel_clk;
+ if (!div) {
+ dev_err(ipu->dev, "invalid pixel clk div = 0\n");
+ return -EINVAL;
+ }
mutex_lock(&ipu->mutex_lock);