diff options
| author | Bruce Allan <bruce.w.allan@intel.com> | 2008-04-23 11:09:00 -0700 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@redhat.com> | 2008-04-25 02:07:11 -0400 |
| commit | 7c25769f88ff0b186766d6a9f9390a2e9fd4670f (patch) | |
| tree | c47607674ec0b14ddfc4f022822f49dbb9b4950f /drivers/net/e1000e/defines.h | |
| parent | c9fcbf4774d7a29b73078017af25d100f152a4af (diff) | |
e1000e: cleanup several stats issues
Several stats registers are completely unused and we just waste pci
bus time reading them. We also omit using the high 32 bits of the GORC/
GOTC counters. We can just read clear them and only read the low registers.
Mii-tool can also break es2lan if it executes a MII PHY register
ioctl while the device is in autonegotiation. Unfortunately it seems
that several applications and installations still perform this ioctl
call periodically and especially in this crucial startup time. We
can fool the ioctl by providing fail safe information that mimics
the "down" link state and only perform the dangerous PHY reads once
after link comes up to fill in the real values. As long as link
stays up the information will not change.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/e1000e/defines.h')
| -rw-r--r-- | drivers/net/e1000e/defines.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 572cfd44397a..4fb9d8722739 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h @@ -527,8 +527,10 @@ #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ /* NVM Control */ #define E1000_EECD_SK 0x00000001 /* NVM Clock */ |