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authorPhil Reid <preid@electromag.com.au>2016-04-07 15:55:35 +0800
committerDavid S. Miller <davem@davemloft.net>2016-04-10 23:44:21 -0400
commit734e00fa02eff5003827abc06a7ebf9449349109 (patch)
tree999638e12bf80aa92ca091ee114c5ef195d0e041 /drivers/net/ethernet/chelsio
parente27260203912b40751fa353d009eaa5a642c739f (diff)
net: stmmac: socfgpa: Ensure emac bit set in System Manger for PTP
When using the PTP fpga to hps clock source for the stmmac module the appropriate bit in the System Manager FPGA Interface Group register needs to be set. This is not set by the bootloader setup when the HPS emac pins are being for this emac module. This allows the PTP clock to be sourced from the FPGA and also connects the PTP pps and ext trig signals to the stmmac PTP hardware. Patch proposed by Phil Collins. Signed-off-by: Phil Reid <preid@electromag.com.au> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/chelsio')
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