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authorPavaluca Matei-B46610 <matei.pavaluca@freescale.com>2014-10-27 10:42:42 +0200
committerDavid S. Miller <davem@davemloft.net>2014-10-29 14:33:15 -0400
commitcf987afc7eb182d04071bed5e2aaea8eb7d17052 (patch)
treee79d5000d777bd6cc8644a23c6a06ff75f70d861 /drivers/net/ethernet/freescale
parent2c6c49ded7a7209fe8618423c457b8000ee528a4 (diff)
Add flow control support flags to gianfar's capabilities
The phy device supports 802.3x flow control, but the specific flags are not set in the phy initialisation code. Flow control flags need to be added to the supported capabilities of the phydev by the driver. This is needed in order for ethtool to work ('ethtool -A' code checks for these flags) Signed-off-by: Pavaluca Matei <matei.pavaluca@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/freescale')
-rw-r--r--drivers/net/ethernet/freescale/gianfar.c3
-rw-r--r--drivers/net/ethernet/freescale/gianfar.h4
2 files changed, 4 insertions, 3 deletions
diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c
index 4fdf0aa16978..2485b742ba70 100644
--- a/drivers/net/ethernet/freescale/gianfar.c
+++ b/drivers/net/ethernet/freescale/gianfar.c
@@ -1687,6 +1687,9 @@ static int init_phy(struct net_device *dev)
priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
priv->phydev->advertising = priv->phydev->supported;
+ /* Add support for flow control, but don't advertise it by default */
+ priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
+
return 0;
}
diff --git a/drivers/net/ethernet/freescale/gianfar.h b/drivers/net/ethernet/freescale/gianfar.h
index 2805cfbf1765..6b008685837c 100644
--- a/drivers/net/ethernet/freescale/gianfar.h
+++ b/drivers/net/ethernet/freescale/gianfar.h
@@ -145,9 +145,7 @@ extern const char gfar_driver_version[];
| SUPPORTED_Autoneg \
| SUPPORTED_MII)
-#define GFAR_SUPPORTED_GBIT (SUPPORTED_1000baseT_Full \
- | SUPPORTED_Pause \
- | SUPPORTED_Asym_Pause)
+#define GFAR_SUPPORTED_GBIT SUPPORTED_1000baseT_Full
/* TBI register addresses */
#define MII_TBICON 0x11