diff options
| author | Fugang Duan <B38611@freescale.com> | 2011-11-02 12:26:49 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-01-09 21:03:58 +0800 |
| commit | d0b74032eb32c50f8b14963ec5178b791bb47704 (patch) | |
| tree | 58ffe6e8934bed3ec76b9b5acc85d461cb7794b1 /drivers/net/fec.h | |
| parent | 76be593514e242ab339894e419128f7d1f68206b (diff) | |
ENGR00161207 - FEC: Add IEEE 1588 driver for imx6
- Support time stamp sync with networking master timer.
- Support ipg 40MHz clock, and precision is about 20ns.
- Don't support ipg 66MHz clock.
- Test flow:
1. Enable CONFIG_FEC_1588 in imx6_defconfig file.
2. Select pll3 for ipg clk 40M in uboot plugin code.
I. set reg 0x20c8028 value to 0x10000;
II.set reg 0x20c8024 value to 0x3040;
III. set reg 0x20c4014[25] to 0x1
IV. set reg 0x20c4014[12:10] to 0x5
3. Rebuid uboot and setup the ethernet environment.
4. Run the 1588 stack ptp_main in master and slave.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'drivers/net/fec.h')
| -rw-r--r-- | drivers/net/fec.h | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/drivers/net/fec.h b/drivers/net/fec.h index 8b2c6d797e6d..1c4063c05ec2 100644 --- a/drivers/net/fec.h +++ b/drivers/net/fec.h @@ -15,7 +15,8 @@ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ - defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) + defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) || \ + defined(CONFIG_ARCH_MX6) /* * Just figures, Motorola would have to change the offsets for * registers in the same peripheral device on different models @@ -47,6 +48,16 @@ #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ +/* Define the FEC 1588 registers offset */ +#if defined(CONFIG_SOC_IMX28) || defined(CONFIG_ARCH_MX6) +#define FEC_ATIME_CTRL 0x400 +#define FEC_ATIME 0x404 +#define FEC_ATIME_EVT_OFFSET 0x408 +#define FEC_ATIME_EVT_PERIOD 0x40c +#define FEC_ATIME_CORR 0x410 +#define FEC_ATIME_INC 0x414 +#define FEC_TS_TIMESTAMP 0x418 +#endif #else #define FEC_ECNTRL 0x000 /* Ethernet control reg */ @@ -76,14 +87,27 @@ #endif /* CONFIG_M5272 */ +#if (defined(CONFIG_SOC_IMX28) || defined(CONFIG_ARCH_MX6)) \ + && defined(CONFIG_FEC_1588) +#define CONFIG_ENHANCED_BD +#endif + /* * Define the buffer descriptor structure. */ -#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) || \ + defined(CONFIG_ARCH_MX6) struct bufdesc { unsigned short cbd_datlen; /* Data length */ unsigned short cbd_sc; /* Control and status info */ unsigned long cbd_bufaddr; /* Buffer address */ +#ifdef CONFIG_ENHANCED_BD + unsigned long cbd_esc; + unsigned long cbd_prot; + unsigned long cbd_bdu; + unsigned long ts; + unsigned short res0[4]; +#endif }; #else struct bufdesc { @@ -126,6 +150,9 @@ struct bufdesc { #define BD_ENET_RX_CL ((ushort)0x0001) #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ +#define BD_ENET_RX_INT 0x00800000 +#define BD_ENET_RX_PTP ((ushort)0x0400) + /* Buffer descriptor control/status used by Ethernet transmit. */ #define BD_ENET_TX_READY ((ushort)0x8000) @@ -143,6 +170,8 @@ struct bufdesc { #define BD_ENET_TX_CSL ((ushort)0x0001) #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ +#define BD_ENET_TX_INT 0x40000000 +#define BD_ENET_TX_PTP ((ushort)0x0100) /****************************************************************************/ #endif /* FEC_H */ |