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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2009-05-24 23:54:30 +0000
committerDavid S. Miller <davem@davemloft.net>2009-05-25 22:49:56 -0700
commit65ac8851490ec97a96759af729132c96f925a795 (patch)
tree3bd4fdb7bb1e46a2f606db89cdbc5df605f6b1f0 /drivers/net/sh_eth.h
parent380af9e390ec81e74a2fd7fad948a8b12eeec7da (diff)
net: sh_eth: Add support SH7724
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sh_eth.h')
-rw-r--r--drivers/net/sh_eth.h58
1 files changed, 56 insertions, 2 deletions
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index eec6c4a7fbe7..9afe5b4c855d 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -40,6 +40,8 @@
#define PKT_BUF_SZ 1538
#if defined(CONFIG_CPU_SUBTYPE_SH7763)
+/* This CPU register maps is very difference by other SH4 CPU */
+
/* Chip Base Address */
# define SH_TSU_ADDR 0xFEE01800
# define ARSTR SH_TSU_ADDR
@@ -141,7 +143,59 @@
# define FWNLCR1 0xB0
# define FWALCR1 0x40
-#else /* #elif defined(CONFIG_CPU_SUBTYPE_SH7763) */
+#elif defined(CONFIG_CPU_SH4) /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */
+/* EtherC */
+#define ECMR 0x100
+#define RFLR 0x108
+#define ECSR 0x110
+#define ECSIPR 0x118
+#define PIR 0x120
+#define PSR 0x128
+#define RDMLR 0x140
+#define IPGR 0x150
+#define APR 0x154
+#define MPR 0x158
+#define TPAUSER 0x164
+#define RFCF 0x160
+#define TPAUSECR 0x168
+#define BCFRR 0x16c
+#define MAHR 0x1c0
+#define MALR 0x1c8
+#define TROCR 0x1d0
+#define CDCR 0x1d4
+#define LCCR 0x1d8
+#define CNDCR 0x1dc
+#define CEFCR 0x1e4
+#define FRECR 0x1e8
+#define TSFRCR 0x1ec
+#define TLFRCR 0x1f0
+#define RFCR 0x1f4
+#define MAFCR 0x1f8
+#define RTRATE 0x1fc
+
+/* E-DMAC */
+#define EDMR 0x000
+#define EDTRR 0x008
+#define EDRRR 0x010
+#define TDLAR 0x018
+#define RDLAR 0x020
+#define EESR 0x028
+#define EESIPR 0x030
+#define TRSCER 0x038
+#define RMFCR 0x040
+#define TFTR 0x048
+#define FDR 0x050
+#define RMCR 0x058
+#define TFUCR 0x064
+#define RFOCR 0x068
+#define FCFTR 0x070
+#define RPADIR 0x078
+#define TRIMD 0x07c
+#define RBWAR 0x0c8
+#define RDFAR 0x0cc
+#define TBRAR 0x0d4
+#define TDFAR 0x0d8
+#else /* #elif defined(CONFIG_CPU_SH4) */
/* This section is SH3 or SH2 */
#ifndef CONFIG_CPU_SUBTYPE_SH7619
/* Chip base address */
@@ -426,7 +480,7 @@ enum FELIC_MODE_BIT {
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
- ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
+ ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
};