diff options
| author | Paul Mackerras <paulus@samba.org> | 2007-05-08 13:37:51 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2007-05-08 13:37:51 +1000 |
| commit | 02bbc0f09c90cefdb2837605c96a66c5ce4ba2e1 (patch) | |
| tree | 04ef573cd4de095c500c9fc3477f4278c0b36300 /drivers/net/tg3.h | |
| parent | 7487a2245b8841c77ba9db406cf99a483b9334e9 (diff) | |
| parent | 5b94f675f57e4ff16c8fda09088d7480a84dcd91 (diff) | |
Merge branch 'linux-2.6'
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index d515ed23841b..4d334cf5a243 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -131,6 +131,7 @@ #define CHIPREV_ID_5752_A0_HW 0x5000 #define CHIPREV_ID_5752_A0 0x6000 #define CHIPREV_ID_5752_A1 0x6001 +#define CHIPREV_ID_5714_A2 0x9002 #define CHIPREV_ID_5906_A1 0xc001 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) #define ASIC_REV_5700 0x07 @@ -1149,6 +1150,9 @@ #define VCPU_STATUS_INIT_DONE 0x04000000 #define VCPU_STATUS_DRV_RESET 0x08000000 +#define VCPU_CFGSHDW 0x00005104 +#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 + /* Mailboxes */ #define GRCMBOX_BASE 0x00005600 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ @@ -1506,6 +1510,8 @@ #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 #define PCIE_TRANS_CFG_LOM 0x00000020 +#define PCIE_PWR_MGMT_THRESH 0x00007d28 +#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 #define TG3_EEPROM_MAGIC 0x669955aa #define TG3_EEPROM_MAGIC_FW 0xa5000000 @@ -1592,6 +1598,9 @@ #define SHASTA_EXT_LED_MAC 0x00010000 #define SHASTA_EXT_LED_COMBO 0x00018000 +#define NIC_SRAM_DATA_CFG_3 0x00000d3c +#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 + #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 @@ -2199,7 +2208,7 @@ struct tg3 { #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 #define TG3_FLAG_ENABLE_ASF 0x00000020 -#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 +#define TG3_FLAG_ASPM_WORKAROUND 0x00000040 #define TG3_FLAG_POLL_SERDES 0x00000080 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 @@ -2215,14 +2224,14 @@ struct tg3 { #define TG3_FLAG_PCI_32BIT 0x00080000 #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 -#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 +#define TG3_FLAG_WOL_CAP 0x00400000 #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 #define TG3_FLAG_10_100_ONLY 0x01000000 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 #define TG3_FLAG_IN_RESET_TASK 0x04000000 #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 -#define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000 +#define TG3_FLAG_SUPPORT_MSI 0x20000000 #define TG3_FLAG_CHIP_RESETTING 0x40000000 #define TG3_FLAG_INIT_COMPLETE 0x80000000 u32 tg3_flags2; @@ -2288,6 +2297,7 @@ struct tg3 { u32 grc_local_ctrl; u32 dma_rwctrl; u32 coalesce_mode; + u32 pwrmgmt_thresh; /* PCI block */ u16 pci_chip_rev_id; |