diff options
| author | Rafał Miłecki <zajec5@gmail.com> | 2010-12-09 20:56:01 +0100 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-12-13 15:23:29 -0500 |
| commit | 42ab135fe78025910bed8ff56e00a375f2b04db1 (patch) | |
| tree | 48062468b386b02beab18aca1caf2621be968845 /drivers/net/wireless/b43/b43.h | |
| parent | d242b90adf4e1918ac86433dfbb32a1136515bdd (diff) | |
b43: rename TMS defines, drop useless condition from core reset
As discussed we do not know band width at core reset time and it is not a good
idea to reset whole just to change band. So just set unconditionally 20 MHz
band width as default during core reset.
As for defines PHY clock changed to band width in specs and it makes much more
sens to call defines by band width which is self-explainable. Updated specs do
not mention 0 value, but comparing to old ones you can notice lineral relation
between PHY clock speed and band width. So it makes sense for 0x0 value to be
10 MHz band width.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43/b43.h')
| -rw-r--r-- | drivers/net/wireless/b43/b43.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h index 9aad2ca3c112..bd4cb75b6ca3 100644 --- a/drivers/net/wireless/b43/b43.h +++ b/drivers/net/wireless/b43/b43.h @@ -416,10 +416,10 @@ enum { /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */ #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ -#define B43_TMSLOW_PHYCLKSPEED 0x00C00000 /* PHY clock speed mask (N-PHY only) */ -#define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x00000000 /* 40 MHz PHY */ -#define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x00400000 /* 80 MHz PHY */ -#define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000 /* 160 MHz PHY */ +#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */ +#define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ +#define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */ +#define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */ #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */ |