diff options
| author | Rafał Miłecki <zajec5@gmail.com> | 2015-01-25 14:39:34 +0100 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2015-01-29 10:54:43 +0200 |
| commit | 86144b01a25185ec092b9301e340ca4f7a8c0d92 (patch) | |
| tree | 4b427ef8ecf1355fe7f73e4ea11a90d9092c5108 /drivers/net/wireless/b43 | |
| parent | 8be08a39d498d5d93ff5149276e34ccb4ec3757f (diff) | |
b43: support bcma core reset on AC-PHY hardware
AC-PHY hardware includes new control 0x3 bits that need to be set to the
0x1 by default.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/b43')
| -rw-r--r-- | drivers/net/wireless/b43/b43.h | 2 | ||||
| -rw-r--r-- | drivers/net/wireless/b43/main.c | 17 |
2 files changed, 19 insertions, 0 deletions
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h index 65b2dd80ecd5..036552439816 100644 --- a/drivers/net/wireless/b43/b43.h +++ b/drivers/net/wireless/b43/b43.h @@ -500,6 +500,8 @@ enum { #define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ #define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */ #define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */ +#define B43_BCMA_IOCTL_PHY_BW_80MHZ 0x000000C0 /* 80 MHz bandwidth */ +#define B43_BCMA_IOCTL_DAC 0x00000300 /* Highspeed DAC mode control field */ #define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */ /* BCMA 802.11 core specific IO status (BCMA_IOST) flags */ diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c index d1c397162a6a..1784933573e4 100644 --- a/drivers/net/wireless/b43/main.c +++ b/drivers/net/wireless/b43/main.c @@ -1262,6 +1262,23 @@ static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode) flags |= B43_BCMA_IOCTL_GMODE; b43_device_enable(dev, flags); + if (dev->phy.type == B43_PHYTYPE_AC) { + u16 tmp; + + tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); + tmp &= ~B43_BCMA_IOCTL_DAC; + tmp |= 0x100; + bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); + + tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); + tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN; + bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); + + tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); + tmp |= B43_BCMA_IOCTL_PHY_CLKEN; + bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); + } + bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST); b43_bcma_phy_reset(dev); bcma_core_pll_ctl(dev->dev->bdev, req, status, true); |