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authorMohamed Abbas <mohamed.abbas@intel.com>2009-05-22 11:01:50 -0700
committerJohn W. Linville <linville@tuxdriver.com>2009-05-22 14:06:05 -0400
commitef850d7cb301bda9155c096269557a4586b58071 (patch)
treee9dc0190a2a575a9515511043805fbdb73ac02e6 /drivers/net/wireless/iwlwifi/iwl-csr.h
parenta2b0f02e4795bfde5f11720a10af8923cb98b654 (diff)
iwlcore: support ICT interrupt
Add ICT interrupt handler support, ICT should improve CPU utilization since it does not require target read which is very expensive. This interrupt handler only added to 5000 cards and newer. Device will write interrupts to ICT shared table to inform driver about its interrupts. These patches will not touch 3945 and 4965 interrupt handlers and tasklet. Signed-off-by: Mohamed Abbas <mohamed.abbas@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-csr.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h
index 3d50ef99f88d..34c123ea1d3e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-csr.h
+++ b/drivers/net/wireless/iwlwifi/iwl-csr.h
@@ -97,6 +97,7 @@
#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
#define CSR_LED_REG (CSR_BASE+0x094)
+#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
/* Analog phase-lock-loop configuration */
@@ -256,6 +257,11 @@
/* HPET MEM debug */
#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
+
+/* DRAM INT TABLE */
+#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
+#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
+
/*=== HBUS (Host-side Bus) ===*/
#define HBUS_BASE (0x400)
/*