diff options
| author | Ivo van Doorn <ivdoorn@gmail.com> | 2008-02-17 17:33:24 +0100 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2008-02-29 15:37:22 -0500 |
| commit | 30b3a23c2594e122e7086f97b5252a87eaf8a817 (patch) | |
| tree | 6c97b928fce785471236543fe71bce3b6d0324cb /drivers/net/wireless/rt2x00/rt2400pci.c | |
| parent | e542239f639fa4e7b13a949d39d44ff1eccf7e3a (diff) | |
rt2x00: Fix Descriptor DMA initialization
As Adam Baker reported the DMA address for the
descriptor base was incorrectly initialized in
the PCI drivers.
Instead of the DMA base for the descriptor, the
DMA base for the data was passed resulting in a
broken TX/RX state for PCI drivers.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
| -rw-r--r-- | drivers/net/wireless/rt2x00/rt2400pci.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c index 52ccb85fed65..28663c00b770 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/rt2x00/rt2400pci.c @@ -597,11 +597,12 @@ static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev, u32 word; rt2x00_desc_read(priv_rx->desc, 2, &word); - rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size); + rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, + entry->queue->data_size); rt2x00_desc_write(priv_rx->desc, 2, word); rt2x00_desc_read(priv_rx->desc, 1, &word); - rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma); + rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); rt2x00_desc_write(priv_rx->desc, 1, word); rt2x00_desc_read(priv_rx->desc, 0, &word); @@ -616,7 +617,7 @@ static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev, u32 word; rt2x00_desc_read(priv_tx->desc, 1, &word); - rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma); + rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma); rt2x00_desc_write(priv_tx->desc, 1, word); rt2x00_desc_read(priv_tx->desc, 2, &word); @@ -648,22 +649,26 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) priv_tx = rt2x00dev->tx[1].entries[0].priv_data; rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); - rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, priv_tx->dma); + rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, + priv_tx->desc_dma); rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); priv_tx = rt2x00dev->tx[0].entries[0].priv_data; rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); - rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma); + rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, + priv_tx->desc_dma); rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); - rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma); + rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, + priv_tx->desc_dma); rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); - rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma); + rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, + priv_tx->desc_dma); rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); @@ -673,7 +678,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) priv_rx = rt2x00dev->rx->entries[0].priv_data; rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); - rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->dma); + rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma); rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); return 0; |