ccwmx51: add support for 2nd ethernet mac

This commit adds support for the second etherent mac.
This driver should be sync with the mainline driver in future.

Signed-off-by: Pedro Perez de Heredia <pedro.perez@digi.com>

4 files changed, 453 insertions, 60 deletions

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index ead8cab3cfe1..9383000211c2 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -249,6 +249,7 @@ obj-$(CONFIG_MACB) += macb.o
 obj-$(CONFIG_S6GMAC) += s6gmac.o
 
 obj-$(CONFIG_ARM) += arm/
+obj-$(CONFIG_SMSC9118) += smsc9118/
 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
 obj-$(CONFIG_TR) += tokenring/
 obj-$(CONFIG_WAN) += wan/
diff --git a/drivers/net/smsc9118/Makefile b/drivers/net/smsc9118/Makefile
new file mode 100644
index 000000000000..d33fe1dc8e38
--- /dev/null
+++ b/drivers/net/smsc9118/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SMSC9118)	+= smsc911x.o
diff --git a/drivers/net/smsc9118/smsc911x.c b/drivers/net/smsc9118/smsc911x.c
index fa1163f7cc6d..e0e7707d9cb2 100644
--- a/drivers/net/smsc9118/smsc911x.c
+++ b/drivers/net/smsc9118/smsc911x.c
@@ -844,7 +844,7 @@ static void smsc911x_phy_update_linkmode(struct net_device *dev, int init)
 	if (mii_check_media(&pdata->mii, netif_msg_link(pdata), init))
 		smsc911x_phy_update_duplex(dev);
 	/* mii_check_media() exists if the media is forced... */
-	if (pdata->mii.force_media) { 
+	if (pdata->mii.force_media) {
 		int cur_link = mii_link_ok(&pdata->mii);
 		int prev_link = netif_carrier_ok(dev);
 
@@ -923,7 +923,7 @@ static int smsc911x_phy_initialise(struct net_device *dev)
 	unsigned int temp;
 
 	printk_debug("Calling phy_initialise()\n");
-	
+
 	pdata->using_extphy = 0;
 
 	switch (pdata->idrev & 0xFFFF0000) {
@@ -1117,7 +1117,7 @@ static int smsc911x_poll(struct napi_struct *napi, int budget)
 			printk_debug("Stopping the RX poll\n");
 			break;
 		}
-		
+
 		pktlength = ((rxstat & 0x3FFF0000) >> 16);
 		pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
 		printk_debug("Going to read %i words (pktlen %i)\n",
@@ -1166,7 +1166,7 @@ static int smsc911x_poll(struct napi_struct *napi, int budget)
 		unsigned int temp;
 		/* We processed all packets available.  Tell NAPI it can
 		 * stop polling then re-enable rx interrupts */
-		netif_rx_complete(dev, napi);
+		napi_complete(napi);
 		temp = smsc911x_reg_read(pdata, INT_EN);
 		temp |= INT_EN_RSFL_EN_;
 		smsc911x_reg_write(temp, pdata, INT_EN);
@@ -1251,7 +1251,7 @@ static int smsc911x_open(struct net_device *dev)
 	unsigned int temp;
 	unsigned int intcfg = 0;
 	struct sockaddr addr;
-  
+
 	/* Reset the LAN911x */
 	smsc911x_reg_write(HW_CFG_SRST_, pdata, HW_CFG);
 	timeout = 10;
@@ -1334,7 +1334,7 @@ static int smsc911x_open(struct net_device *dev)
 
 	printk_debug("IRQ handler passed test using IRQ %d\n", dev->irq);
 	netif_carrier_off(dev);
-	
+
 	if (!smsc911x_phy_initialise(dev)) {
 		printk_err("Failed to initialize the PHY");
 		return -ENODEV;
@@ -1377,7 +1377,7 @@ static int smsc911x_open(struct net_device *dev)
 	memcpy(addr.sa_data, dev->dev_addr, dev->addr_len);
 	if(smsc911x_set_mac(dev, &addr))
 		printk_err("Couldn't set the MAC address.\n");
-	
+
 	netif_start_queue(dev);
 	return 0;
 }
@@ -1388,7 +1388,7 @@ static int smsc911x_stop(struct net_device *dev)
 	struct smsc911x_data *pdata = netdev_priv(dev);
 
 	printk_info("Stopping the interface\n");
-	
+
 	napi_disable(&pdata->napi);
 
 	/* disable interrupts */
@@ -1405,7 +1405,7 @@ static int smsc911x_stop(struct net_device *dev)
 
 	/* Stop sending data after the last transmission */
 	smsc911x_reg_write(TX_CFG_STOP_TX_, pdata, TX_CFG);
-	
+
 	SMSC_TRACE("Interface stopped");
 	return 0;
 }
@@ -1579,8 +1579,8 @@ static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
 	if ((intcfg & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) != (INT_CFG_IRQ_INT_ |
 								INT_CFG_IRQ_EN_))
 		return serviced;
-	
-	
+
+
 	if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
 		temp = smsc911x_reg_read(pdata, INT_EN);
 		temp &= (~INT_EN_SW_INT_EN_);
@@ -1618,12 +1618,12 @@ static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
 	}
 
 	if (likely(intsts & inten & INT_STS_RSFL_)) {
-		if (likely(netif_rx_schedule_prep(dev, &pdata->napi))) {
+		if (likely(napi_schedule_prep(&pdata->napi))) {
 			/* Disable Rx interrupts and schedule NAPI poll */
 			temp = smsc911x_reg_read(pdata, INT_EN);
 			temp &= (~INT_EN_RSFL_EN_);
 			smsc911x_reg_write(temp, pdata, INT_EN);
-			__netif_rx_schedule(dev, &pdata->napi);
+			__napi_schedule(&pdata->napi);
 		}
 
 		serviced = IRQ_HANDLED;
@@ -1687,9 +1687,10 @@ smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
 static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
 					struct ethtool_drvinfo *info)
 {
-	strncpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
-	strncpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
-	strncpy(info->bus_info, dev->dev.bus_id, sizeof(info->bus_info));
+	strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
+	strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
+	strlcpy(info->bus_info, dev_name(dev->dev.parent),
+		sizeof(info->bus_info));
 }
 
 static int smsc911x_ethtool_nwayreset(struct net_device *dev)
@@ -1862,14 +1863,14 @@ static int smsc911x_ethtool_set_wol(struct net_device *dev,
 				    struct ethtool_wolinfo *wol)
 {
 	struct smsc911x_data *pdata;
-	
+
 	/* Check for unsupported options */
         if (wol->wolopts & (WAKE_MAGICSECURE | WAKE_UCAST | WAKE_MCAST
 			    | WAKE_BCAST | WAKE_ARP))
                 return -EINVAL;
 
 	pdata = netdev_priv(dev);
-		
+
 	/* When disable the WOL options need to disable the PHY-interrupts too */
 	if (!wol->wolopts) {
 		printk_pmdbg("[ WOL  ] Disabling all sources\n");
@@ -1934,7 +1935,7 @@ static int smsc911x_set_mac(struct net_device *dev, void *addr)
 	struct smsc911x_data *pdata;
 	unsigned int low, high;
 	struct sockaddr *paddr = addr;
-	
+
 	printk_debug("Set mac called\n");
 
 	pdata = netdev_priv(dev);
@@ -1958,7 +1959,7 @@ static int smsc911x_set_mac(struct net_device *dev, void *addr)
 	/* Now set the high address */
 	smsc911x_reg_write(high, pdata, MAC_CSR_DATA);
 	smsc911x_reg_write(ADDRH | MAC_CSR_CMD_CSR_BUSY_, pdata, MAC_CSR_CMD);
-	reg = smsc911x_reg_read(pdata, BYTE_TEST);	
+	reg = smsc911x_reg_read(pdata, BYTE_TEST);
 	if (!smsc911x_mac_notbusy(pdata)) {
 		retval = -EBUSY;
 		goto exit_unlock;
@@ -1967,7 +1968,7 @@ static int smsc911x_set_mac(struct net_device *dev, void *addr)
 	/* First set the low address */
 	smsc911x_reg_write(low, pdata, MAC_CSR_DATA);
 	smsc911x_reg_write(ADDRL | MAC_CSR_CMD_CSR_BUSY_, pdata, MAC_CSR_CMD);
-	reg = smsc911x_reg_read(pdata, BYTE_TEST);	
+	reg = smsc911x_reg_read(pdata, BYTE_TEST);
 	if (!smsc911x_mac_notbusy(pdata)) {
 		retval = -EBUSY;
 		goto exit_unlock;
@@ -1975,19 +1976,31 @@ static int smsc911x_set_mac(struct net_device *dev, void *addr)
 
 	/* And save the IP inside the driver structure */
 	memcpy(dev->dev_addr, paddr->sa_data, dev->addr_len);
-	
+
 	printk_debug("MAC successful changed to %02X%08X\n",
 		     smsc911x_mac_read(pdata, ADDRH),
 		     smsc911x_mac_read(pdata, ADDRL));
-	
+
 	retval = 0;
-	
+
  exit_unlock:
 	spin_unlock_irqrestore(&pdata->phy_lock, flags);
-	
+
 	return retval;
 }
 
+static const struct net_device_ops smsc911x_netdev_ops = {
+	.ndo_open		= smsc911x_open,
+	.ndo_stop		= smsc911x_stop,
+	.ndo_start_xmit		= smsc911x_hard_start_xmit,
+	.ndo_get_stats		= smsc911x_get_stats,
+	.ndo_set_multicast_list	= smsc911x_set_multicast_list,
+	.ndo_do_ioctl		= smsc911x_do_ioctl,
+	.ndo_set_mac_address 	= smsc911x_set_mac,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller	= smsc911x_poll_controller,
+#endif
+};
 /* Initializing private device structures */
 static int smsc911x_init(struct net_device *dev)
 {
@@ -2212,21 +2225,11 @@ static int smsc911x_init(struct net_device *dev)
 			     "for this chip revision");
 
 	ether_setup(dev);
-	dev->open = smsc911x_open;
-	dev->stop = smsc911x_stop;
-	dev->hard_start_xmit = smsc911x_hard_start_xmit;
-	dev->get_stats = smsc911x_get_stats;
-	dev->set_multicast_list = smsc911x_set_multicast_list;
 	dev->flags |= IFF_MULTICAST;
-	dev->do_ioctl = smsc911x_do_ioctl;
-	dev->set_mac_address = smsc911x_set_mac;
-	netif_napi_add(dev, &pdata->napi, smsc911x_poll, 64);
+	netif_napi_add(dev, &pdata->napi, smsc911x_poll, 64);//SMSC_NAPI_WEIGHT
+	dev->netdev_ops = &smsc911x_netdev_ops;
 	dev->ethtool_ops = &smsc911x_ethtool_ops;
 
-#ifdef CONFIG_NET_POLL_CONTROLLER
-	dev->poll_controller = smsc911x_poll_controller;
-#endif				/* CONFIG_NET_POLL_CONTROLLER */
-
 	pdata->mii.phy_id_mask = 0x1f;
 	pdata->mii.reg_num_mask = 0x1f;
 	pdata->mii.force_media = 0;
@@ -2321,6 +2324,7 @@ static int smsc911x_drv_probe(struct platform_device *pdev)
 		struct smc911x_platdata *config = pdev->dev.platform_data;
 		pdata->irq_polarity = config->irq_polarity;
 		pdata->irq_flags  = config->irq_flags;
+		pdata->irq_type = config->irq_type;
 	}
 
 	if (pdata->ioaddr == NULL) {
@@ -2337,11 +2341,6 @@ static int smsc911x_drv_probe(struct platform_device *pdev)
 	if (pdata->irq_polarity)
 		intcfg |= INT_CFG_IRQ_POL_;
 
-	/*
-	 * @XXX: The "irq_type" is not used at this moment, because we are using
-	 * the same platform-data as the driver from the Vanilla-kernel.
-	 * (Luis Galdos)
-	 */
 	if (pdata->irq_type)
 		intcfg |= INT_CFG_IRQ_TYPE_;
 
@@ -2403,7 +2402,7 @@ static int smsc911x_drv_probe(struct platform_device *pdev)
 		    dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
 
         /* Enable the wakeup over this device (Luis Galdos) */
-        device_init_wakeup(&pdev->dev, 1); 
+        device_init_wakeup(&pdev->dev, 1);
         device_set_wakeup_enable(&pdev->dev, 0);
 	return 0;
 
@@ -2435,7 +2434,7 @@ static int smsc911x_drv_state_wakeup(struct smsc911x_data *pdata, int mode)
 
 	if (mode != 1 && mode != 2)
 		return -EINVAL;
-	
+
 	/* Clear already received WUs */
 	regval = smsc911x_mac_read(pdata, WUCSR);
 	regval &= ~(WUCSR_MPR_ | WUCSR_WUFR_);
@@ -2451,12 +2450,12 @@ static int smsc911x_drv_state_wakeup(struct smsc911x_data *pdata, int mode)
 
 	if (mode /* @FIXME: Enabled only for D2 */) {
 		u16 phy_mode;
-		
+
 		phy_mode = smsc911x_phy_read(pdata, MII_INTMSK);
                 phy_mode |= PHY_INTMSK_ENERGYON_;
                 smsc911x_phy_write(pdata, MII_INTMSK, phy_mode);
 	}
-	
+
         /* Clear the PM mode and clear the current wakeup status */
 	regval = smsc911x_reg_read(pdata, PMT_CTRL);
 	regval &= ~PMT_CTRL_PM_MODE_;
@@ -2484,7 +2483,7 @@ static int smsc911x_drv_state_wakeup(struct smsc911x_data *pdata, int mode)
 static int smsc911x_drv_state_d2(struct smsc911x_data *pdata)
 {
 	unsigned long regval;
-	
+
 	/* Disable the interrupts of the controller */
 	regval = smsc911x_reg_read(pdata, INT_CFG);
 	regval &= ~INT_CFG_IRQ_EN_;
@@ -2518,11 +2517,11 @@ static int smsc911x_drv_suspend(struct platform_device *pdev, pm_message_t state
 
        if (!ndev)
                return -ENODEV;
-       
+
        /* @FIXME: Implement the other supported power modes of the smsc911x */
         if (state.event != PM_EVENT_SUSPEND)
                 return -ENOTSUPP;
-       
+
        if (netif_running(ndev)) {
 
                /* The below code is coming from the WinCE guys */
@@ -2533,7 +2532,7 @@ static int smsc911x_drv_suspend(struct platform_device *pdev, pm_message_t state
 		* detection using the standard IRQ-line
 		*/
 	       if (device_may_wakeup(&pdev->dev)) {
-		       
+
 		       /*
 			* Sanity check for verifying that a wakeup-source was
 			* configured from the user space. If the energy-detect
@@ -2545,7 +2544,7 @@ static int smsc911x_drv_suspend(struct platform_device *pdev, pm_message_t state
 			       retval = -EINVAL;
 			       goto err_attach;
 		       }
-		       
+
 		       /*
 			* By the WOL (magic packet, etc.) we can ONLY use the D1, but
 			* for the energy detect over the PHY we can change into D2
@@ -2558,7 +2557,7 @@ static int smsc911x_drv_suspend(struct platform_device *pdev, pm_message_t state
 			       printk_pmdbg("[ SUSP ] Preparing D2 with wakeup\n");
 			       smsc911x_drv_state_wakeup(pdata, 2);
 		       }
-		       
+
 		       enable_irq_wake(ndev->irq);
 
 	       } else {
@@ -2569,7 +2568,7 @@ static int smsc911x_drv_suspend(struct platform_device *pdev, pm_message_t state
 		       smsc911x_drv_state_d2(pdata);
 	       }
        }
-       
+
        return 0;
 
 err_attach:
@@ -2592,7 +2591,7 @@ static int smsc911x_drv_resume(struct platform_device *pdev)
                 if (netif_running(ndev)) {
                        unsigned long timeout;
                        unsigned long regval, pmt_ctrl;
-                       
+
                        /* Assert the byte test register for waking up */
                        smsc911x_reg_write(0x0, pdata, BYTE_TEST);
 
@@ -2627,12 +2626,12 @@ static int smsc911x_drv_resume(struct platform_device *pdev)
 			       regval &= ~(PMT_CTRL_WOL_EN_ | PMT_CTRL_PME_EN_ |
 					   PMT_CTRL_ED_EN_);
 			       smsc911x_reg_write(regval, pdata, PMT_CTRL);
-			       
+
 			       /* Disable the PM interrupts */
 			       regval =  smsc911x_reg_read(pdata, INT_EN);
 			       regval &= ~(INT_EN_PME_INT_EN_ | INT_EN_PHY_INT_EN_);
 			       smsc911x_reg_write(regval, pdata, INT_EN);
-			       
+
 			       /* Disable the wakeup-events on the MAC */
 			       regval = smsc911x_mac_read(pdata, WUCSR);
 			       regval &= ~(WUCSR_MPEN_);
@@ -2642,13 +2641,13 @@ static int smsc911x_drv_resume(struct platform_device *pdev)
 		       /* @XXX: Clear only the interrupts that were generated */
 		       regval = (INT_STS_PME_INT_ | INT_STS_PHY_INT_);
 		       smsc911x_reg_write(regval, pdata, INT_STS);
-		       
+
 		       /* Set the controller into the state D0 */
                        regval = smsc911x_reg_read(pdata, PMT_CTRL);
                        regval &= ~PMT_CTRL_PM_MODE_;
 		       regval |= PMT_CTRL_PM_MODE_D0_;
                        smsc911x_reg_write(regval, pdata, PMT_CTRL);
-		       
+
                        /* Paranoic sanity checks */
                        regval = smsc911x_reg_read(pdata, PMT_CTRL);
                        if (regval & PMT_CTRL_PM_MODE_)
@@ -2659,7 +2658,7 @@ static int smsc911x_drv_resume(struct platform_device *pdev)
                                printk_err("Device is still NOT ready.\n");
 			       goto exit_resume;
 		       }
-                       
+
                        regval = smsc911x_phy_read(pdata, MII_BMCR);
                        regval &= ~BMCR_PDOWN;
                        smsc911x_phy_write(pdata, MII_BMCR, regval);
@@ -2671,7 +2670,7 @@ static int smsc911x_drv_resume(struct platform_device *pdev)
 
 		       /* Reset the wakeup control and status register */
 		       smsc911x_mac_write(pdata, WUCSR, 0x00);
-		       
+
 		       netif_device_attach(ndev);
                 }
         }
diff --git a/drivers/net/smsc9118/smsc911x.h b/drivers/net/smsc9118/smsc911x.h
new file mode 100644
index 000000000000..75bb3252b866
--- /dev/null
+++ b/drivers/net/smsc9118/smsc911x.h
@@ -0,0 +1,392 @@
+/***************************************************************************
+ *
+ * Copyright (C) 2004-2007  SMSC
+ * Copyright (C) 2005 ARM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ ***************************************************************************/
+#ifndef __SMSC911X_H__
+#define __SMSC911X_H__
+
+#if defined(CONFIG_MACH_CC9M2443JS) || defined(CONFIG_MACH_CCW9M2443JS) || \
+    defined(CONFIG_MACH_CCWMX51JS) || defined(CONFIG_MACH_CCMX51JS)
+# define SMSC_CAN_USE_32BIT	0
+#else
+# define SMSC_CAN_USE_32BIT	1
+#endif
+
+#define TX_FIFO_LOW_THRESHOLD	(u32)1600
+#define SMSC911X_EEPROM_SIZE	(u32)7
+#define USE_DEBUG 		0
+//#define USE_DEBUG 		2
+
+/* implements a PHY loopback test at initialisation time, to ensure a packet
+ * can be succesfully looped back */
+#define USE_PHY_WORK_AROUND
+
+/* 10/100 LED link-state inversion when media is disconnected */
+/* #define USE_LED1_WORK_AROUND */
+
+/* platform_device configuration data, should be assigned to
+ * the platform_device's dev.platform_data */
+struct smsc911x_platform_config {
+	unsigned int irq_polarity;
+	unsigned int irq_type;
+};
+
+#if USE_DEBUG >= 1
+#define SMSC_WARNING(fmt, args...) \
+		printk(KERN_EMERG "SMSC_WARNING: %s: " fmt "\n", \
+			__FUNCTION__ , ## args)
+#else
+#define SMSC_WARNING(msg, args...)
+#endif				/* USE_DEBUG >= 1 */
+
+#if USE_DEBUG >= 2
+#define SMSC_TRACE(fmt,args...) \
+		printk(KERN_EMERG "SMSC_TRACE: %s: " fmt "\n", \
+			__FUNCTION__ , ## args)
+#else
+#define SMSC_TRACE(msg, args...)
+#endif				/* USE_DEBUG >= 2 */
+
+/* SMSC911x registers and bitfields */
+#define RX_DATA_FIFO			0x00
+
+#define TX_DATA_FIFO			0x20
+#define TX_CMD_A_ON_COMP_		0x80000000
+#define TX_CMD_A_BUF_END_ALGN_		0x03000000
+#define TX_CMD_A_4_BYTE_ALGN_		0x00000000
+#define TX_CMD_A_16_BYTE_ALGN_		0x01000000
+#define TX_CMD_A_32_BYTE_ALGN_		0x02000000
+#define TX_CMD_A_DATA_OFFSET_		0x001F0000
+#define TX_CMD_A_FIRST_SEG_		0x00002000
+#define TX_CMD_A_LAST_SEG_		0x00001000
+#define TX_CMD_A_BUF_SIZE_		0x000007FF
+#define TX_CMD_B_PKT_TAG_		0xFFFF0000
+#define TX_CMD_B_ADD_CRC_DISABLE_	0x00002000
+#define TX_CMD_B_DISABLE_PADDING_	0x00001000
+#define TX_CMD_B_PKT_BYTE_LENGTH_	0x000007FF
+
+#define RX_STATUS_FIFO			0x40
+#define RX_STS_ES_			0x00008000
+#define RX_STS_MCAST_			0x00000400
+
+#define RX_STATUS_FIFO_PEEK		0x44
+
+#define TX_STATUS_FIFO			0x48
+#define TX_STS_ES_			0x00008000
+
+#define TX_STATUS_FIFO_PEEK		0x4C
+
+#define ID_REV				0x50
+#define ID_REV_CHIP_ID_			0xFFFF0000
+#define ID_REV_REV_ID_			0x0000FFFF
+
+#define INT_CFG				0x54
+#define INT_CFG_INT_DEAS_		0xFF000000
+#define INT_CFG_INT_DEAS_CLR_		0x00004000
+#define INT_CFG_INT_DEAS_STS_		0x00002000
+#define INT_CFG_IRQ_INT_		0x00001000
+#define INT_CFG_IRQ_EN_			0x00000100
+#define INT_CFG_IRQ_POL_		0x00000010
+#define INT_CFG_IRQ_TYPE_		0x00000001
+
+#define INT_STS				0x58
+#define INT_STS_SW_INT_			0x80000000
+#define INT_STS_TXSTOP_INT_		0x02000000
+#define INT_STS_RXSTOP_INT_		0x01000000
+#define INT_STS_RXDFH_INT_		0x00800000
+#define INT_STS_RXDF_INT_		0x00400000
+#define INT_STS_TX_IOC_			0x00200000
+#define INT_STS_RXD_INT_		0x00100000
+#define INT_STS_GPT_INT_		0x00080000
+#define INT_STS_PHY_INT_		0x00040000
+#define INT_STS_PME_INT_		0x00020000
+#define INT_STS_TXSO_			0x00010000
+#define INT_STS_RWT_			0x00008000
+#define INT_STS_RXE_			0x00004000
+#define INT_STS_TXE_			0x00002000
+#define INT_STS_TDFU_			0x00000800
+#define INT_STS_TDFO_			0x00000400
+#define INT_STS_TDFA_			0x00000200
+#define INT_STS_TSFF_			0x00000100
+#define INT_STS_TSFL_			0x00000080
+#define INT_STS_RXDF_			0x00000040
+#define INT_STS_RDFL_			0x00000020
+#define INT_STS_RSFF_			0x00000010
+#define INT_STS_RSFL_			0x00000008
+#define INT_STS_GPIO2_INT_		0x00000004
+#define INT_STS_GPIO1_INT_		0x00000002
+#define INT_STS_GPIO0_INT_		0x00000001
+
+#define INT_EN				0x5C
+#define INT_EN_SW_INT_EN_		0x80000000
+#define INT_EN_TXSTOP_INT_EN_		0x02000000
+#define INT_EN_RXSTOP_INT_EN_		0x01000000
+#define INT_EN_RXDFH_INT_EN_		0x00800000
+#define INT_EN_TIOC_INT_EN_		0x00200000
+#define INT_EN_RXD_INT_EN_		0x00100000
+#define INT_EN_GPT_INT_EN_		0x00080000
+#define INT_EN_PHY_INT_EN_		0x00040000
+#define INT_EN_PME_INT_EN_		0x00020000
+#define INT_EN_TXSO_EN_			0x00010000
+#define INT_EN_RWT_EN_			0x00008000
+#define INT_EN_RXE_EN_			0x00004000
+#define INT_EN_TXE_EN_			0x00002000
+#define INT_EN_TDFU_EN_			0x00000800
+#define INT_EN_TDFO_EN_			0x00000400
+#define INT_EN_TDFA_EN_			0x00000200
+#define INT_EN_TSFF_EN_			0x00000100
+#define INT_EN_TSFL_EN_			0x00000080
+#define INT_EN_RXDF_EN_			0x00000040
+#define INT_EN_RDFL_EN_			0x00000020
+#define INT_EN_RSFF_EN_			0x00000010
+#define INT_EN_RSFL_EN_			0x00000008
+#define INT_EN_GPIO2_INT_		0x00000004
+#define INT_EN_GPIO1_INT_		0x00000002
+#define INT_EN_GPIO0_INT_		0x00000001
+
+#define BYTE_TEST			0x64
+
+#define FIFO_INT			0x68
+#define FIFO_INT_TX_AVAIL_LEVEL_	0xFF000000
+#define FIFO_INT_TX_STS_LEVEL_		0x00FF0000
+#define FIFO_INT_RX_AVAIL_LEVEL_	0x0000FF00
+#define FIFO_INT_RX_STS_LEVEL_		0x000000FF
+
+#define RX_CFG				0x6C
+#define RX_CFG_RX_END_ALGN_		0xC0000000
+#define RX_CFG_RX_END_ALGN4_		0x00000000
+#define RX_CFG_RX_END_ALGN16_		0x40000000
+#define RX_CFG_RX_END_ALGN32_		0x80000000
+#define RX_CFG_RX_DMA_CNT_		0x0FFF0000
+#define RX_CFG_RX_DUMP_			0x00008000
+#define RX_CFG_RXDOFF_			0x00001F00
+
+#define TX_CFG				0x70
+#define TX_CFG_TXS_DUMP_		0x00008000
+#define TX_CFG_TXD_DUMP_		0x00004000
+#define TX_CFG_TXSAO_			0x00000004
+#define TX_CFG_TX_ON_			0x00000002
+#define TX_CFG_STOP_TX_			0x00000001
+
+#define HW_CFG				0x74
+#define HW_CFG_TTM_			0x00200000
+#define HW_CFG_SF_			0x00100000
+#define HW_CFG_TX_FIF_SZ_		0x000F0000
+#define HW_CFG_TR_			0x00003000
+#define HW_CFG_SRST_			0x00000001
+
+/* only available on 115/117 */
+#define HW_CFG_PHY_CLK_SEL_		0x00000060
+#define HW_CFG_PHY_CLK_SEL_INT_PHY_	0x00000000
+#define HW_CFG_PHY_CLK_SEL_EXT_PHY_	0x00000020
+#define HW_CFG_PHY_CLK_SEL_CLK_DIS_	0x00000040
+#define HW_CFG_SMI_SEL_		 	0x00000010
+#define HW_CFG_EXT_PHY_DET_		0x00000008
+#define HW_CFG_EXT_PHY_EN_		0x00000004
+#define HW_CFG_SRST_TO_			0x00000002
+
+/* only available  on 116/118 */
+#define HW_CFG_32_16_BIT_MODE_		0x00000004
+
+#define RX_DP_CTRL			0x78
+#define RX_DP_CTRL_RX_FFWD_		0x80000000
+
+#define RX_FIFO_INF			0x7C
+#define RX_FIFO_INF_RXSUSED_		0x00FF0000
+#define RX_FIFO_INF_RXDUSED_		0x0000FFFF
+
+#define TX_FIFO_INF			0x80
+#define TX_FIFO_INF_TSUSED_		0x00FF0000
+#define TX_FIFO_INF_TDFREE_		0x0000FFFF
+
+#define PMT_CTRL			0x84
+#define PMT_CTRL_PM_MODE_		0x00003000
+#define PMT_CTRL_PM_MODE_D0_		0x00000000
+#define PMT_CTRL_PM_MODE_D1_		0x00001000
+#define PMT_CTRL_PM_MODE_D2_		0x00002000
+#define PMT_CTRL_PM_MODE_D3_		0x00003000
+#define PMT_CTRL_PHY_RST_		0x00000400
+#define PMT_CTRL_WOL_EN_		0x00000200
+#define PMT_CTRL_ED_EN_			0x00000100
+#define PMT_CTRL_PME_TYPE_		0x00000040
+#define PMT_CTRL_WUPS_			0x00000030
+#define PMT_CTRL_WUPS_NOWAKE_		0x00000000
+#define PMT_CTRL_WUPS_ED_		0x00000010
+#define PMT_CTRL_WUPS_WOL_		0x00000020
+#define PMT_CTRL_WUPS_MULTI_		0x00000030
+#define PMT_CTRL_PME_IND_		0x00000008
+#define PMT_CTRL_PME_POL_		0x00000004
+#define PMT_CTRL_PME_EN_		0x00000002
+#define PMT_CTRL_READY_			0x00000001
+
+#define GPIO_CFG			0x88
+#define GPIO_CFG_LED3_EN_		0x40000000
+#define GPIO_CFG_LED2_EN_		0x20000000
+#define GPIO_CFG_LED1_EN_		0x10000000
+#define GPIO_CFG_GPIO2_INT_POL_		0x04000000
+#define GPIO_CFG_GPIO1_INT_POL_		0x02000000
+#define GPIO_CFG_GPIO0_INT_POL_		0x01000000
+#define GPIO_CFG_EEPR_EN_		0x00700000
+#define GPIO_CFG_GPIOBUF2_		0x00040000
+#define GPIO_CFG_GPIOBUF1_		0x00020000
+#define GPIO_CFG_GPIOBUF0_		0x00010000
+#define GPIO_CFG_GPIODIR2_		0x00000400
+#define GPIO_CFG_GPIODIR1_		0x00000200
+#define GPIO_CFG_GPIODIR0_		0x00000100
+#define GPIO_CFG_GPIOD4_		0x00000020
+#define GPIO_CFG_GPIOD3_		0x00000010
+#define GPIO_CFG_GPIOD2_		0x00000004
+#define GPIO_CFG_GPIOD1_		0x00000002
+#define GPIO_CFG_GPIOD0_		0x00000001
+
+#define GPT_CFG				0x8C
+#define GPT_CFG_TIMER_EN_		0x20000000
+#define GPT_CFG_GPT_LOAD_		0x0000FFFF
+
+#define GPT_CNT				0x90
+#define GPT_CNT_GPT_CNT_		0x0000FFFF
+
+#define ENDIAN				0x98
+
+#define FREE_RUN			0x9C
+
+#define RX_DROP				0xA0
+
+#define MAC_CSR_CMD			0xA4
+#define MAC_CSR_CMD_CSR_BUSY_		0x80000000
+#define MAC_CSR_CMD_R_NOT_W_		0x40000000
+#define MAC_CSR_CMD_CSR_ADDR_		0x000000FF
+
+#define MAC_CSR_DATA			0xA8
+
+#define AFC_CFG				0xAC
+#define AFC_CFG_AFC_HI_			0x00FF0000
+#define AFC_CFG_AFC_LO_			0x0000FF00
+#define AFC_CFG_BACK_DUR_		0x000000F0
+#define AFC_CFG_FCMULT_			0x00000008
+#define AFC_CFG_FCBRD_			0x00000004
+#define AFC_CFG_FCADD_			0x00000002
+#define AFC_CFG_FCANY_			0x00000001
+
+#define E2P_CMD				0xB0
+#define E2P_CMD_EPC_BUSY_		0x80000000
+#define E2P_CMD_EPC_CMD_		0x70000000
+#define E2P_CMD_EPC_CMD_READ_		0x00000000
+#define E2P_CMD_EPC_CMD_EWDS_		0x10000000
+#define E2P_CMD_EPC_CMD_EWEN_		0x20000000
+#define E2P_CMD_EPC_CMD_WRITE_		0x30000000
+#define E2P_CMD_EPC_CMD_WRAL_		0x40000000
+#define E2P_CMD_EPC_CMD_ERASE_		0x50000000
+#define E2P_CMD_EPC_CMD_ERAL_		0x60000000
+#define E2P_CMD_EPC_CMD_RELOAD_		0x70000000
+#define E2P_CMD_EPC_TIMEOUT_		0x00000200
+#define E2P_CMD_MAC_ADDR_LOADED_	0x00000100
+#define E2P_CMD_EPC_ADDR_		0x000000FF
+
+#define E2P_DATA			0xB4
+#define E2P_DATA_EEPROM_DATA_		0x000000FF
+#define LAN_REGISTER_EXTENT		0x00000100
+
+/*
+ * MAC Control and Status Register (Indirect Address)
+ * Offset (through the MAC_CSR CMD and DATA port)
+ */
+#define MAC_CR				0x01
+#define MAC_CR_RXALL_			0x80000000
+#define MAC_CR_HBDIS_			0x10000000
+#define MAC_CR_RCVOWN_			0x00800000
+#define MAC_CR_LOOPBK_			0x00200000
+#define MAC_CR_FDPX_			0x00100000
+#define MAC_CR_MCPAS_			0x00080000
+#define MAC_CR_PRMS_			0x00040000
+#define MAC_CR_INVFILT_			0x00020000
+#define MAC_CR_PASSBAD_			0x00010000
+#define MAC_CR_HFILT_			0x00008000
+#define MAC_CR_HPFILT_			0x00002000
+#define MAC_CR_LCOLL_			0x00001000
+#define MAC_CR_BCAST_			0x00000800
+#define MAC_CR_DISRTY_			0x00000400
+#define MAC_CR_PADSTR_			0x00000100
+#define MAC_CR_BOLMT_MASK_		0x000000C0
+#define MAC_CR_DFCHK_			0x00000020
+#define MAC_CR_TXEN_			0x00000008
+#define MAC_CR_RXEN_			0x00000004
+
+#define ADDRH				0x02
+
+#define ADDRL				0x03
+
+#define HASHH				0x04
+
+#define HASHL				0x05
+
+#define MII_ACC				0x06
+#define MII_ACC_PHY_ADDR_		0x0000F800
+#define MII_ACC_MIIRINDA_		0x000007C0
+#define MII_ACC_MII_WRITE_		0x00000002
+#define MII_ACC_MII_BUSY_		0x00000001
+
+#define MII_DATA			0x07
+
+#define FLOW				0x08
+#define FLOW_FCPT_			0xFFFF0000
+#define FLOW_FCPASS_			0x00000004
+#define FLOW_FCEN_			0x00000002
+#define FLOW_FCBSY_			0x00000001
+
+#define VLAN1				0x09
+
+#define VLAN2				0x0A
+
+#define WUFF				0x0B
+
+#define WUCSR				0x0C
+#define WUCSR_GUE_			0x00000200
+#define WUCSR_WUFR_			0x00000040
+#define WUCSR_MPR_			0x00000020
+#define WUCSR_WAKE_EN_			0x00000004
+#define WUCSR_MPEN_			0x00000002
+
+/*
+ * Phy definitions (vendor-specific)
+ */
+#define LAN9118_PHY_ID			0x00C0001C
+
+#define MII_INTSTS			0x1D
+
+#define MII_INTMSK			0x1E
+#define PHY_INTMSK_AN_RCV_		(1 << 1)
+#define PHY_INTMSK_PDFAULT_		(1 << 2)
+#define PHY_INTMSK_AN_ACK_		(1 << 3)
+#define PHY_INTMSK_LNKDOWN_		(1 << 4)
+#define PHY_INTMSK_RFAULT_		(1 << 5)
+#define PHY_INTMSK_AN_COMP_		(1 << 6)
+#define PHY_INTMSK_ENERGYON_		(1 << 7)
+#define PHY_INTMSK_DEFAULT_		(PHY_INTMSK_ENERGYON_ | \
+					 PHY_INTMSK_AN_COMP_ | \
+					 PHY_INTMSK_RFAULT_ | \
+					 PHY_INTMSK_LNKDOWN_)
+
+#define ADVERTISE_PAUSE_ALL		(ADVERTISE_PAUSE_CAP | \
+					 ADVERTISE_PAUSE_ASYM)
+
+#define LPA_PAUSE_ALL			(LPA_PAUSE_CAP | \
+					 LPA_PAUSE_ASYM)
+
+#endif				/* __SMSC911X_H__ */