diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2017-07-27 15:58:27 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:27:44 +0800 |
| commit | 2cbb044389bc6af78917bc051d41bc057a954bfe (patch) | |
| tree | 22f10e6a215e7cc5262599f04fc272c3660fb7d3 /drivers/pci | |
| parent | 99da31240de0b8a0ff113cc03fe3e24c7d1d1f7a (diff) | |
MLK-16052-2 PCI: imx: fix the pcieb link down issue
The calibration value of PCIEA is mandatory required
by PCIEB on iMX8QM.
The RSTs of the PCIEA would be cleared when the PDs
of PCIEA are turned off.
The calibration value of PCIEA would be lost when the
RSTs of PCIEA are cleared.
So, the RSTs of PCIEA should be asserted when enable
the PCIEB port. Otherwise, PCIEB wouldn't be functional.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/dwc/pci-imx6.c | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index f786015f775b..819b1c735cc5 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -410,6 +410,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) { struct device *dev = imx6_pcie->pci->dev; u32 val; + int i; switch (imx6_pcie->variant) { case IMX6SX: @@ -439,19 +440,21 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), BIT(2)); break; case IMX8QM: - val = IMX8QM_CSR_PCIEA_OFFSET + imx6_pcie->ctrl_id * SZ_64K; - regmap_update_bits(imx6_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_BUTTON_RST_N, - IMX8QM_CTRL_BUTTON_RST_N); - regmap_update_bits(imx6_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_PERST_N, - IMX8QM_CTRL_PERST_N); - regmap_update_bits(imx6_pcie->iomuxc_gpr, - val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, - IMX8QM_CTRL_POWER_UP_RST_N, - IMX8QM_CTRL_POWER_UP_RST_N); + for (i = 0; i <= imx6_pcie->ctrl_id; i++) { + val = IMX8QM_CSR_PCIEA_OFFSET + i * SZ_64K; + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); + regmap_update_bits(imx6_pcie->iomuxc_gpr, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); + } break; case IMX8MQ: if (imx6_pcie->ctrl_id == 0) |