diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2016-10-18 17:35:21 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:09 +0800 |
| commit | b7576d5afc4ffd767c1fbd0be195e6732ec9a311 (patch) | |
| tree | 78dad10128c717dfa3b1fe2503325a920de5fe48 /drivers/pci | |
| parent | a40fd13be4dbf2590dd411b1b7f977965ad6b33c (diff) | |
MLK-13365 pci: imx: fix imx6dl ep rc validation failure
The ep rc validation is failed on imx6dl.
Root cause:
The ref clk of imx6dl pcie is 100M(bit20 of PLL_ENET).
But the driver doesn't enable it.
Solution:
enable pci_bus clock in ep rc validation system, since
the parent of the pci_bus is the 100M.
The connection between ep and rc only have the TX/RX
parirs, there is no impaction when enable the pcie_bus
in pcie ep rc validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/dwc/pci-imx6.c | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index 8eccfa4948b6..3b2ae15f6290 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -449,22 +449,19 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) goto err_pcie; } - if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS) && - !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) { - if (imx6_pcie->ext_osc) { - clk_set_parent(imx6_pcie->pcie_ext, - imx6_pcie->pcie_ext_src); - ret = clk_prepare_enable(imx6_pcie->pcie_ext); - if (ret) { - dev_err(dev, "unable to enable pcie_ext clock\n"); - goto err_pcie_bus; - } - } else { - ret = clk_prepare_enable(imx6_pcie->pcie_bus); - if (ret) { - dev_err(dev, "unable to enable pcie_bus clock\n"); - goto err_pcie_bus; - } + if (imx6_pcie->ext_osc) { + clk_set_parent(imx6_pcie->pcie_ext, + imx6_pcie->pcie_ext_src); + ret = clk_prepare_enable(imx6_pcie->pcie_ext); + if (ret) { + dev_err(dev, "unable to enable pcie_ext clock\n"); + goto err_pcie_bus; + } + } else { + ret = clk_prepare_enable(imx6_pcie->pcie_bus); + if (ret) { + dev_err(dev, "unable to enable pcie_bus clock\n"); + goto err_pcie_bus; } } @@ -552,9 +549,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) err_ref_clk: clk_disable_unprepare(imx6_pcie->pcie_phy); err_pcie_phy: - if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS) - && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS) - && !imx6_pcie->ext_osc) + if (!imx6_pcie->ext_osc) clk_disable_unprepare(imx6_pcie->pcie_bus); err_pcie_bus: clk_disable_unprepare(imx6_pcie->pcie); @@ -662,7 +657,8 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) if (!IS_ENABLED(CONFIG_PCI_IMX6_COMPLIANCE_TEST)) { clk_disable_unprepare(imx6_pcie->pcie); - clk_disable_unprepare(imx6_pcie->pcie_bus); + if (!imx6_pcie->ext_osc) + clk_disable_unprepare(imx6_pcie->pcie_bus); clk_disable_unprepare(imx6_pcie->pcie_phy); if (imx6_pcie->variant == IMX6SX) clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); |