diff options
| author | Jay Agarwal <jagarwal@nvidia.com> | 2013-12-06 17:43:07 +0530 |
|---|---|---|
| committer | Jay Agarwal <jagarwal@nvidia.com> | 2013-12-09 04:22:47 -0800 |
| commit | 4093d8834195c184bfe76c5a4ecd771ccf45e11b (patch) | |
| tree | 2f5d2ce62a8642c46851c5b897f24809be2e3428 /drivers/pci | |
| parent | ad90b49ffa6705e364868cb6b2fe3b4303ccaccd (diff) | |
ARM: tegra: pcie: Enable Rootport AER support
Enable AER Support for Rootports by programming
its private registers
Bug 1259524
Change-Id: Ia9d2e5dbcdac1d3e8af114d152be5059518e6eb1
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/339209
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 58894d1ae701..b8a6b85b4849 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -209,6 +209,9 @@ #define NV_PCIE2_RP_VEND_XP1 0x00000F04 #define NV_PCIE2_RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT (1 << 21) +#define NV_PCIE2_RP_VEND_CTL1 0x00000F48 +#define PCIE2_RP_VEND_CTL1_ERPT (1 << 13) + #define NV_PCIE2_RP_VEND_XP_BIST 0x00000F4C #define PCIE2_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) @@ -1476,6 +1479,11 @@ static void tegra_pcie_enable_rp_features(int index) data |= PCIE2_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; rp_writel(data, NV_PCIE2_RP_VEND_XP_BIST, index); + /* unhide AER capability */ + data = rp_readl(NV_PCIE2_RP_VEND_CTL1, index); + data |= PCIE2_RP_VEND_CTL1_ERPT; + rp_writel(data, NV_PCIE2_RP_VEND_CTL1, index); + tegra_pcie_apply_sw_war(index); } @@ -1698,7 +1706,7 @@ static void tegra_pcie_pll_pdn(void) } /* Enable ASPM support of all devices based on it's capability */ -static void tegra_pcie_enable_aspm_support(void) +static void tegra_pcie_enable_aspm(void) { struct pci_dev *pdev = NULL; u16 val = 0, aspm = 0; @@ -1725,7 +1733,7 @@ static void tegra_pcie_enable_features(void) pr_info("PCIE: Link speed change failed\n"); tegra_pcie_pll_pdn(); - tegra_pcie_enable_aspm_support(); + tegra_pcie_enable_aspm(); } static int __init tegra_pcie_init(void) |