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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2015-02-04 18:02:55 +0900
committerBjorn Helgaas <bhelgaas@google.com>2015-02-24 00:24:12 -0600
commitecd06305c9a077ab5aa000cb8027e2c1c872f25f (patch)
treefc2b90e6c940cbe2f20b61b260ffaa49ea39cd92 /drivers/pci
parent2ea2a2734cd850d8d270022e9aaabc02a931c172 (diff)
PCI: rcar: Change PCIEPARL and PCIEPARH to PCIEPALR and PCIEPAUR
PCIEPARL and PCIEPARH are macros that calculate register addresses. However, the register names are incorrect. Change them to PCIEPALR and PCIEPAUR. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pcie-rcar.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index a910f795bfee..c086210f2ffd 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -64,8 +64,8 @@
#define LAR_ENABLE (1 << 1)
/* PCIe address reg & mask */
-#define PCIEPARL(x) (0x03400 + ((x) * 0x20))
-#define PCIEPARH(x) (0x03404 + ((x) * 0x20))
+#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
+#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
#define PAR_ENABLE (1 << 31)
@@ -341,9 +341,9 @@ static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
else
res_start = res->start;
- rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPARH(win));
+ rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
- PCIEPARL(win));
+ PCIEPALR(win));
/* First resource is for IO */
mask = PAR_ENABLE;