diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2019-05-07 13:11:14 +0800 |
|---|---|---|
| committer | Joakim Zhang <qiangqing.zhang@nxp.com> | 2019-05-14 09:12:53 +0800 |
| commit | 525cce9da853fbf231c0dee64d202db31597aa6f (patch) | |
| tree | 83c600c0846c521a544e11adf6f49a2b03b96fd7 /drivers/perf | |
| parent | f0e9f058af055c7aa34f6c4475a4183e655f4453 (diff) | |
MLK-21289 perf: ddr-perf: calculate ddr bandwidth via virtual event read-bytes/write-bytes
We can calculate ddr bandwidth via virtual event read-bytes/write-bytes based
on ddr burst width, which actually share event read-cycles/write-cycles. Burst
width is 32 bit on i.MX8 board till now.
The ddr interface will generate 2 up edges and 2 down edges in an internal
clock cycle, so it can pass 4 beats of data. 4 bytes of each beat if ddr
burst width is 32 bit.
Cmd bellow:
perf stat -a -e ddr0/read-bytes/ ls
perf stat -a -e ddr0/write-bytes/ ls
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/ddr-perf.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/perf/ddr-perf.c b/drivers/perf/ddr-perf.c index cd338cb5f64a..7374a094b439 100644 --- a/drivers/perf/ddr-perf.c +++ b/drivers/perf/ddr-perf.c @@ -69,7 +69,13 @@ PMU_EVENT_ATTR_STRING(lp-req-nocredit, ddr_perf_lp_req_nocredit, "event=0x26"); PMU_EVENT_ATTR_STRING(lp-xact-credit, ddr_perf_lp_xact_credit, "event=0x27"); PMU_EVENT_ATTR_STRING(wr-xact-credit, ddr_perf_wr_xact_credit, "event=0x29"); PMU_EVENT_ATTR_STRING(read-cycles, ddr_perf_read_cycles, "event=0x2a"); +PMU_EVENT_ATTR_STRING(read-bytes, ddr_perf_read_bytes, "event=0xf2a"); +PMU_EVENT_ATTR_STRING(read-bytes.unit, ddr_perf_read_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(read-bytes.scale, ddr_perf_read_bytes_scale, "0.000016"); PMU_EVENT_ATTR_STRING(write-cycles, ddr_perf_write_cycles, "event=0x2b"); +PMU_EVENT_ATTR_STRING(write-bytes, ddr_perf_write_bytes, "event=0xf2b"); +PMU_EVENT_ATTR_STRING(write-bytes.unit, ddr_perf_write_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(write-bytes.scale, ddr_perf_write_bytes_scale, "0.000016"); PMU_EVENT_ATTR_STRING(read-write-transition, ddr_perf_read_write_transition, "event=0x30"); PMU_EVENT_ATTR_STRING(precharge, ddr_perf_precharge, "event=0x31"); @@ -154,7 +160,13 @@ static struct attribute *ddr_perf_events_attrs[] = { &ddr_perf_lp_xact_credit.attr.attr, &ddr_perf_wr_xact_credit.attr.attr, &ddr_perf_read_cycles.attr.attr, + &ddr_perf_read_bytes.attr.attr, + &ddr_perf_read_bytes_unit.attr.attr, + &ddr_perf_read_bytes_scale.attr.attr, &ddr_perf_write_cycles.attr.attr, + &ddr_perf_write_bytes.attr.attr, + &ddr_perf_write_bytes_unit.attr.attr, + &ddr_perf_write_bytes_scale.attr.attr, &ddr_perf_read_write_transition.attr.attr, &ddr_perf_precharge.attr.attr, &ddr_perf_activate.attr.attr, |