diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2019-12-31 16:29:40 +0800 |
|---|---|---|
| committer | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-01-07 10:32:56 +0800 |
| commit | 0a2228ab23785fbee1d37e6a6f840be0c4dfeb4e (patch) | |
| tree | 652258f29333c0ac8a2ae455d204021fda8ee378 /drivers/perf | |
| parent | 05d68c514f824747fe2b04ac92b4567c1d1ee347 (diff) | |
MLK-23195-3 perf/imx_ddr: speed up overflow frequency of cycle counter
For i.MX8MP, we cannot ensure that cycle counter overflow occurs at
least 4 times as often as other events. Due to byte counters will count for
any event configured, it will overflow more often. And if byte counters
oveflow that related counters would stop since they share the
COUNTER_CNTL. We can speed up cycle counter overflow frequency by
setting counter parameter(CP) field of cycle counter.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/fsl_imx8_ddr_perf.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index abd003592ff7..b29b4b0636da 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -29,6 +29,8 @@ #define CNTL_CLEAR_MASK 0xFFFFFFFD #define CNTL_OVER_MASK 0xFFFFFFFE +#define CNTL_CP_SHIFT 16 +#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) #define CNTL_CSV_SHIFT 24 #define CNTL_CSV_MASK (0xFF << CNTL_CSV_SHIFT) @@ -401,6 +403,20 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; val |= FIELD_PREP(CNTL_CSV_MASK, config); + + /* + * Workaround for i.MX8MP: + * Common counters and byte counters share the same COUNTER_CNTL, + * and byte counters could overflow before cycle counter. Need set + * counter parameter(CP) of cycle counter to give it initial value + * which can speed up cycle counter overflow frequency. + */ + if ((pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) == + DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + val |= FIELD_PREP(CNTL_CP_MASK, 0xe8); + } + writel(val, pmu->base + reg); } else { /* Disable counter */ |