diff options
| author | Shaokun Zhang <zhangshaokun@hisilicon.com> | 2020-06-05 17:43:41 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-06-24 17:50:41 +0200 |
| commit | a98132826820dec082bb57d5d733aa57bbcae6fc (patch) | |
| tree | 1fce8d42abcee21c5bef9758b552160c4b4d1c50 /drivers/perf | |
| parent | e1ee6238534e514268bc373f03fb398ac0c8a9d0 (diff) | |
drivers/perf: hisi: Fix wrong value for all counters enable
[ Upstream commit 961abd78adcb4c72c343fcd9f9dc5e2ebbe9b448 ]
In L3C uncore PMU drivers, bit16 is used to control all counters enable &
disable. Wrong value is given in the driver and its default value is 1'b1,
it can work because each PMU counter has its own control bits too.
Let's fix the wrong value.
Fixes: 2940bc433370 ("perf: hisi: Add support for HiSilicon SoC L3C PMU driver")
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/1591350221-32275-1-git-send-email-zhangshaokun@hisilicon.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c index 078b8dc57250..c5b0950c2a7a 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -35,7 +35,7 @@ /* L3C has 8-counters */ #define L3C_NR_COUNTERS 0x8 -#define L3C_PERF_CTRL_EN 0x20000 +#define L3C_PERF_CTRL_EN 0x10000 #define L3C_EVTYPE_NONE 0xff /* |