diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-02-24 13:08:05 +0800 |
|---|---|---|
| committer | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-02-25 09:58:31 +0800 |
| commit | befb57153a10db396fb4eedb8a01c5cbf2aa2ef2 (patch) | |
| tree | 40926b996a56bd4d74a0febb1d85dc1b5d4be032 /drivers/perf | |
| parent | d056a461709f3a125559fff37963503320aaa6a9 (diff) | |
MLK-23372 perf/imx_ddr: correct CLEAR bit definition
ddr_perf_event_stop will firstly call ddr_perf_counter_enable to disable
the counter, and then call ddr_perf_event_update to read the counter value.
When disable the counter, it will write 0 into COUNTER_CNTL[CLEAR] bit
which cause the counter value cleared. Counter value will always be 0
when update the counter.
The correct definition of CLEAR bit is that write 0 to clear the counter
value.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/fsl_imx8_ddr_perf.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index b29b4b0636da..ff8a8659f721 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -396,9 +396,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, if (enable) { /* - * must disable first, then enable again - * otherwise, cycle counter will not work - * if previous state is enabled. + * cycle counter is special which should firstly write 0 then + * write 1 into CLEAR bit to clear it. Other counters only + * need write 0 into CLEAR bit and it turns out to be 1 by + * hardware. Below enable flow is harmless for all counters. */ writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; @@ -420,7 +421,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(val, pmu->base + reg); } else { /* Disable counter */ - writel(0, pmu->base + reg); + val = readl(pmu->base + reg) & CNTL_EN_MASK; + writel(val, pmu->base + reg); } } |