diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2017-12-05 09:24:24 +0200 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 29e9b38686c11c77f52fcae5735ce5858995920b (patch) | |
| tree | 16d33840273d53451ff01b13a48bb90c363ea545 /drivers/phy | |
| parent | 073788db3daf9a9a6f051224c001c319fc296f7a (diff) | |
MLK-16986-1: phy: Fix Mixel PHY driver best_match
When setting up the CM, CN and CO decimal values for DPHY PLL, these
values should only be rounded up when a "best_match" is requested. Some
DSI receivers requires the DSI clock to be exactly matched with the
pixel clock.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/phy-mixel-mipi-dsi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/phy/phy-mixel-mipi-dsi.c b/drivers/phy/phy-mixel-mipi-dsi.c index cd7192da076b..0b004002f9c0 100644 --- a/drivers/phy/phy-mixel-mipi-dsi.c +++ b/drivers/phy/phy-mixel-mipi-dsi.c @@ -146,7 +146,8 @@ int mixel_phy_mipi_set_phy_speed(struct phy *phy, if (numerator < 16 || numerator > 255) return -EINVAL; - numerator = DIV_ROUND_UP(numerator, denominator) * denominator; + if (best_match) + numerator = DIV_ROUND_UP(numerator, denominator) * denominator; priv->divider.cn = 1; if (denominator > 8) { |