diff options
| author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> | 2017-03-31 10:29:19 -0500 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 62a36b35009da76a7e815f95189c201e66504d1e (patch) | |
| tree | a32a990ac1ae5b220276d33e0131fab871b955cd /drivers/pinctrl/freescale | |
| parent | b1a8d7376fec55843ffdc7109e12425aae5ca89f (diff) | |
MLK-14599-1 soc:imx8:Update SCFW API
Update SCFW API to the following commit in SCFW git:
"
'commit: ("a620caf7444c45715b68b5cf128219005598365f")'
Author: Mike <michael.kjar@nxp.com>
Date: Thu Mar 30 18:35:27 2017 -0500
Added a DDR Stress Test to the test folder
- New DDR test is like the stress test where we increment/sweep the DDR freq
- More tests may be added as development continues
- Modified mx8qm/soc.h to boot the A72 to DDR when building with option qmddr
"
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Diffstat (limited to 'drivers/pinctrl/freescale')
| -rw-r--r-- | drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c index 440baec10635..9bd6ee04ed5e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -49,7 +49,7 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { IMX_PINCTRL_PIN(SC_P_EMMC0_DATA7), IMX_PINCTRL_PIN(SC_P_EMMC0_STROBE), IMX_PINCTRL_PIN(SC_P_EMMC0_RESET_B), - IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX), + IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0), IMX_PINCTRL_PIN(SC_P_USDHC1_RESET_B), IMX_PINCTRL_PIN(SC_P_USDHC1_VSELECT), IMX_PINCTRL_PIN(SC_P_USDHC1_WP), @@ -74,7 +74,7 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD1), IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD2), IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD3), - IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB), + IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0), IMX_PINCTRL_PIN(SC_P_ENET0_REFCLK_125M_25M), IMX_PINCTRL_PIN(SC_P_ENET0_MDIO), IMX_PINCTRL_PIN(SC_P_ENET0_MDC), @@ -85,8 +85,6 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { IMX_PINCTRL_PIN(SC_P_FLEXCAN1_TX), IMX_PINCTRL_PIN(SC_P_UART0_RX), IMX_PINCTRL_PIN(SC_P_UART0_TX), - IMX_PINCTRL_PIN(SC_P_UART0_RTS_B), - IMX_PINCTRL_PIN(SC_P_UART0_CTS_B), IMX_PINCTRL_PIN(SC_P_UART1_TX), IMX_PINCTRL_PIN(SC_P_UART1_RX), IMX_PINCTRL_PIN(SC_P_UART1_RTS_B), @@ -101,13 +99,9 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { IMX_PINCTRL_PIN(SC_P_SPI2_SDO), IMX_PINCTRL_PIN(SC_P_SPI2_SDI), IMX_PINCTRL_PIN(SC_P_SPI2_CS0), - IMX_PINCTRL_PIN(SC_P_SPI2_CS1), IMX_PINCTRL_PIN(SC_P_SAI1_RXC), IMX_PINCTRL_PIN(SC_P_SAI1_RXD), IMX_PINCTRL_PIN(SC_P_SAI1_RXFS), - IMX_PINCTRL_PIN(SC_P_SAI1_TXC), - IMX_PINCTRL_PIN(SC_P_SAI1_TXD), - IMX_PINCTRL_PIN(SC_P_SAI1_TXFS), IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT), IMX_PINCTRL_PIN(SC_P_ESAI0_FSR), IMX_PINCTRL_PIN(SC_P_ESAI0_FST), @@ -129,7 +123,6 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { IMX_PINCTRL_PIN(SC_P_SPI3_CS1), IMX_PINCTRL_PIN(SC_P_MCLK_IN0), IMX_PINCTRL_PIN(SC_P_MCLK_OUT0), - IMX_PINCTRL_PIN(SC_P_FTM0), IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB), IMX_PINCTRL_PIN(SC_P_ADC_IN1), IMX_PINCTRL_PIN(SC_P_ADC_IN0), @@ -189,15 +182,6 @@ static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = { IMX_PINCTRL_PIN(SC_P_QSPI0B_DQS), IMX_PINCTRL_PIN(SC_P_QSPI0B_SS0_B), IMX_PINCTRL_PIN(SC_P_QSPI0B_SS1_B), - IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0), - IMX_PINCTRL_PIN(SC_P_XTALI), - IMX_PINCTRL_PIN(SC_P_XTALO), - IMX_PINCTRL_PIN(SC_P_ANA_TEST_OUT_P), - IMX_PINCTRL_PIN(SC_P_ANA_TEST_OUT_N), - IMX_PINCTRL_PIN(SC_P_RTC_XTALI), - IMX_PINCTRL_PIN(SC_P_RTC_XTALO), - IMX_PINCTRL_PIN(SC_P_PMIC_ON_REQ), - IMX_PINCTRL_PIN(SC_P_ON_OFF_BUTTON), }; static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = { |