Merge tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pincontrol updates from Linus Walleij:
 :This is the bulk of pin control changes for the v3.20 cycle:

  Framework changes and enhancements:
   - Passing -DDEBUG recursively to subdir drivers so we get debug
     messages properly turned on.
   - Infer map type from DT property in the groups parsing code in the
     generic pinconfig code.
   - Support for custom parameter passing in generic pin config.  This
     is used when you are using the generic pin config, but want to add
     a few custom properties that no other driver will use.

  New drivers:
   - Driver for the Xilinx Zynq
   - Driver for the AmLogic Meson SoCs

  New features in drivers:
   - Sleep support (suspend/resume) for the Cherryview driver
   - mvebeu a38x can now mux a UART on pins MPP19 and MPP20
   - Migrated the qualcomm driver to generic pin config handling of
     extended config options in the core code.
   - Support BUS1 and AUDIO in the Exynos pin controller.
   - Add some missing functions in the sun6i driver.
   - Add support for the A31S variant in the sun6i driver.
   - EMEv2 support in the Renesas PFC driver.
   - Add support for Qualcomm MSM8916 in the qcom driver.

  Deleted features
   - Drop support for the SiRF Marco that was never released to the
     market.
   - Drop SH7372 support as the support for this platform is removed
     from the kernel"

* tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits)
  sh-pfc: emev2 - Fix mangled author name
  pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs
  pinctrl: imx25: fix numbering for pins
  pinctrl: pinctrl-imx: don't use invalid value of conf_reg
  pinctrl: qcom: delete pin_config_get/set pinconf operations
  pinctrl: qcom: Add msm8916 pinctrl driver
  DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding
  pinctrl: qcom: increase variable size for register offsets
  pinctrl: hide PCONFDUMP in #ifdef
  pinctrl: rockchip: Only mask interrupts; never disable
  pinctrl: zynq: Fix usb0 pins
  pinctrl: sh-pfc: sh7372: Remove DT binding documentation
  pinctrl: sh-pfc: sh7372: Remove PFC support
  sh-pfc: Add emev2 pinmux support
  sh-pfc: add macro to define pinmux without function
  pinctrl: add driver for Amlogic Meson SoCs
  staging: drivers: pinctrl: Fixed checkpatch.pl warnings
  pinctrl: exynos: Add AUDIO pin controller for exynos7
  sh-pfc: r8a7790: add MLB+ pin group
  sh-pfc: r8a7791: add MLB+ pin group
  ...

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
index 1d21dc226920..0b0fc2eb48e0 100644
--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -101,6 +101,7 @@ static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
 	for (i = 0; i < len; i++) {
 		/* strlen("ioXYZ") + 1 = 6 */
 		char *name = kzalloc(6, GFP_KERNEL);
+
 		snprintf(name, 6, "io%d", base + i);
 		d[i].number = base + i;
 		d[i].name = name;
@@ -463,7 +464,7 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
 								   &res);
 		if (IS_ERR(falcon_info.membase[*bank]))
 			return PTR_ERR(falcon_info.membase[*bank]);
-		
+
 		avail = pad_r32(falcon_info.membase[*bank],
 					LTQ_PADC_AVAIL);
 		pins = fls(avail);