MLK-14946-2: pinctrl: imx8qm/qxp: switch to use new format

switch to use new format. Split mux out from pad config.
Change the high two bits in pad config to 0, because driver
will automatically set that two bits to 1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

3 files changed, 18 insertions, 9 deletions

diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index df12a08e4694..7642e3102289 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -118,8 +118,8 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
 			new_map[j].data.configs.group_or_pin =
 					pin_get_name(pctldev, pin->pin);
 			new_map[j].data.configs.configs =
-					(unsigned long *)&pin->pin_conf.pin_scu.all;
-			new_map[j].data.configs.num_configs = 1;
+					(unsigned long *)&pin->pin_conf.pin_scu;
+			new_map[j].data.configs.num_configs = 2;
 			j++;
 		} else if (!(pin->pin_conf.pin_memmap.config & IMX_NO_PAD_CTL)) {
 			new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
@@ -318,7 +318,7 @@ static const struct pinconf_ops imx_pinconf_ops = {
  * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
  * 1 u32 CONFIG, so 24 types in total for each pin.
  */
-#define FSL_IMX8_PIN_SIZE 8
+#define FSL_IMX8_PIN_SIZE 12
 #define FSL_PIN_SIZE 24
 #define SHARE_FSL_PIN_SIZE 20
 
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index f915bf93aef4..d2c6d7502839 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -40,7 +40,8 @@ struct imx_pin_memmap {
 };
 
 struct imx_pin_scu {
-	unsigned int all;
+	unsigned long mux;
+	unsigned long config;
 };
 
 struct imx_pin {
diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c
index 7a629baacf22..7759cf9dc6cb 100644
--- a/drivers/pinctrl/freescale/pinctrl-scu.c
+++ b/drivers/pinctrl/freescale/pinctrl-scu.c
@@ -61,7 +61,12 @@ int imx_pinconf_backend_set(struct pinctrl_dev *pctldev, unsigned pin_id,
 	sc_ipc_t ipc = pinctrl_ipcHandle;
 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
-	unsigned int val = configs[0];
+	/*
+	 * Mux should be done in pmx set, but we do not have a good api
+	 * to handle that in scfw, so config it in pad conf func
+	 */
+	unsigned int mux = configs[0];
+	unsigned int val = configs[1];
 
 	if (ipc == -1) {
 		printk("IPC handle not initialized!\n");
@@ -74,8 +79,10 @@ int imx_pinconf_backend_set(struct pinctrl_dev *pctldev, unsigned pin_id,
 	if (info->flags & IMX8_ENABLE_PAD_CONFIG)
 		val |= BM_IMX8_GP_ENABLE;
 
-	if (info->flags & SHARE_MUX_CONF_REG)
+	if (info->flags & SHARE_MUX_CONF_REG) {
+		val |= (mux << 27) & (0x7 << 27);
 		err = sc_pad_set(ipc, pin_id, val);
+	}
 
 	if (err != SC_ERR_NONE)
 		return -EIO;
@@ -91,10 +98,11 @@ int imx_pinctrl_parse_pin(struct imx_pinctrl_soc_info *info,
 
 	pin->pin = be32_to_cpu(*((*list_p)++));
 	*pin_id = pin->pin;
-	pin_scu->all = be32_to_cpu(*((*list_p)++));
+	pin_scu->mux = be32_to_cpu(*((*list_p)++));
+	pin_scu->config = be32_to_cpu(*((*list_p)++));
 
-	dev_dbg(info->dev, "%s: 0x%x",
-		 info->pins[pin->pin].name, pin_scu->all);
+	dev_dbg(info->dev, "%s: 0x%lx 0x%lx",
+		 info->pins[pin->pin].name, pin_scu->mux, pin_scu->config);
 
 	return 0;
 }