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authorBai Ping <ping.bai@nxp.com>2016-05-16 13:38:02 +0800
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-24 12:41:33 +0300
commit35859ee25badc02416ac0a570ed1d5019e7f9619 (patch)
treee997c596b9abc681498bde50294d310b9e9ccea7 /drivers/pinctrl
parentcac6e9e69b97c7d23d4783fe6b811dce019a1f96 (diff)
MLK-12796-01 pinctrl: imx: Add iomuxc_snvs pinctrl driver for i.mx6ull
On i.MX6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL register have been moved from IOMUXC to IOMUXC_SNVS, so the pinctrl driver should be modified to support the IOMUXC_SNVS. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6ul.c52
1 files changed, 50 insertions, 2 deletions
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
index 1aeb840aae1d..cbad1c69226d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
@@ -150,6 +150,21 @@ enum imx6ul_pads {
MX6UL_PAD_CSI_DATA07 = 128,
};
+enum imx6ull_lpsr_pads {
+ MX6ULL_PAD_BOOT_MODE0 = 0,
+ MX6ULL_PAD_BOOT_MODE1 = 1,
+ MX6ULL_PAD_SNVS_TAMPER0 = 2,
+ MX6ULL_PAD_SNVS_TAMPER1 = 3,
+ MX6ULL_PAD_SNVS_TAMPER2 = 4,
+ MX6ULL_PAD_SNVS_TAMPER3 = 5,
+ MX6ULL_PAD_SNVS_TAMPER4 = 6,
+ MX6ULL_PAD_SNVS_TAMPER5 = 7,
+ MX6ULL_PAD_SNVS_TAMPER6 = 8,
+ MX6ULL_PAD_SNVS_TAMPER7 = 9,
+ MX6ULL_PAD_SNVS_TAMPER8 = 10,
+ MX6ULL_PAD_SNVS_TAMPER9 = 11,
+};
+
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
@@ -283,20 +298,53 @@ static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
};
+/* pad for i.MX6ULL lpsr pinmux */
+static struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8),
+ IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9),
+};
+
static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
.pins = imx6ul_pinctrl_pads,
.npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
.gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
};
+static struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = {
+ .pins = imx6ull_snvs_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads),
+ .flags = ZERO_OFFSET_VALID,
+};
+
static struct of_device_id imx6ul_pinctrl_of_match[] = {
- { .compatible = "fsl,imx6ul-iomuxc", },
+ { .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, },
+ { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
{ /* sentinel */ }
};
static int imx6ul_pinctrl_probe(struct platform_device *pdev)
{
- return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info);
+ const struct of_device_id *match;
+ struct imx_pinctrl_soc_info *pinctrl_info;
+
+ match = of_match_device(imx6ul_pinctrl_of_match, &pdev->dev);
+
+ if (!match)
+ return -ENODEV;
+
+ pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;
+
+ return imx_pinctrl_probe(pdev, pinctrl_info);
}
static struct platform_driver imx6ul_pinctrl_driver = {