diff options
author | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2025-06-19 08:37:27 +0200 |
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committer | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2025-06-19 10:55:50 +0200 |
commit | 3bb604cef85fb366931a777a20579cc7c24b6c5c (patch) | |
tree | 855a4c90b2b093047060d9a5c5888a27e68e54cd /drivers/pwm/pwm-mediatek.c | |
parent | 1e78582cc49cd07d726ea073178625c1cbbed013 (diff) | |
parent | 58485ff1a74f6c5be9e7c6aafb7293e4337348e7 (diff) |
Merge tag 'v6.1.141' into toradex_ti-linux-6.1.y
This is the 6.1.141 stable release
Conflicts:
drivers/spi/spi-cadence-quadspi.c
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Diffstat (limited to 'drivers/pwm/pwm-mediatek.c')
-rw-r--r-- | drivers/pwm/pwm-mediatek.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index a337b47dc2f7..10c2ed23f551 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -120,21 +120,25 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, reg_thres = PWMTHRES; + unsigned long clk_rate; u64 resolution; int ret; ret = pwm_mediatek_clk_enable(chip, pwm); - if (ret < 0) return ret; + clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); + if (!clk_rate) + return -EINVAL; + /* Make sure we use the bus clock and not the 26MHz clock */ if (pc->soc->has_ck_26m_sel) writel(0, pc->regs + PWM_CK_26M_SEL); /* Using resolution in picosecond gets accuracy higher */ resolution = (u64)NSEC_PER_SEC * 1000; - do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); + do_div(resolution, clk_rate); cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); while (cnt_period > 8191) { |