diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2017-12-15 16:15:12 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <helgaas@kernel.org> | 2018-02-15 18:41:06 -0600 |
| commit | 7babfa5b4bf0a9574c9b30f657b1d87abc5a84cf (patch) | |
| tree | 6c29f45f730b80569fbf674dcd51389474761593 /drivers/rapidio | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
rapidio/tsi721: use PCI_EXP_DEVCTL2_COMP_TIMEOUT macro
Use the existing PCI_EXP_DEVCTL2_COMP_TIMEOUT macro instead of hard-coding
the PCIe Completion Timeout Value mask. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Alexandre Bounine <alexandre.bounine@idt.com>
Diffstat (limited to 'drivers/rapidio')
| -rw-r--r-- | drivers/rapidio/devices/tsi721.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c index 9a68914100ad..bb655854713d 100644 --- a/drivers/rapidio/devices/tsi721.c +++ b/drivers/rapidio/devices/tsi721.c @@ -2880,8 +2880,9 @@ static int tsi721_probe(struct pci_dev *pdev, "Invalid MRRS override value %d", pcie_mrrs); } - /* Adjust PCIe completion timeout. */ - pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2); + /* Set PCIe completion timeout to 1-10ms */ + pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0x2); /* * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block |