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| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2011-02-18 18:31:54 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:51:59 -0700 |
| commit | a5371fd54e8fdc79558d0478c3147a3b514fe20e (patch) | |
| tree | 0bc8596833c8e794c77303186d8cd48383054e6a /drivers/serial/m32r_sio.h | |
| parent | 61e9c07d871b22f6d0be6799b5620f4da948edea (diff) | |
ARM: tegra: cardhu:Use PLL_C for sdmmc1
PLL_C can generate 208 MHz clock for SDMMC1.
SD 3.0 cards can work at 208 MHz. Increase sdmmc1
frequency to 208 MHz.
Bug 661035
Original-Change-Id: I7afa110de4d77183c959a53b1fab31fdec37e193
Reviewed-on: http://git-master/r/20045
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I46dbac5135c5419a93d05285aa46acaf2601efc2
Diffstat (limited to 'drivers/serial/m32r_sio.h')
0 files changed, 0 insertions, 0 deletions